Hello Joe,
Le 28/01/15 04:22, Joe Britton a écrit :
I was thinking that the high-level interface would look as close as
possible to that for the PDQ DACs. See attached PDFs for the waveform
description language that we use in our current .dc files. -Joe
Ok agreed for the low-level API then.
On 01/27/2015 03:48 AM, Yann Sionneau wrote:
Actually I was thinking about using the PyDAQmx project (
http://pythonhosted.org/PyDAQmx/ ) and provide a direct access to the PyDAQmx
API through the ARTIQ RPC mechanism.
The PyDAQmx API being itself a direct wrapping/binding of the NI DAQ mx
Thank you for the question Yann. I spoke with John Gabler and Dan Slichter
here at NIST and came up with the following advice.
There's no need for the 6733 controller to run on a Linux machine. I've
found the NI libraries on Windows to be reasonably straightforward
(NI-DAQmx libraries with C++).
Does the FPGA need to generate one pulse per DAC sample?
Yes, one pulse is required per sample. One way of doing this might be to
have a fixed frequency clock that is gated by a RTIO channel.
On Wed, Jan 21, 2015 at 7:46 PM, Sébastien Bourdeauducq s...@m-labs.hk
wrote:
On 01/22/2015 02:08 AM,
On 01/22/2015 02:08 AM, Joe Britton wrote:
* The waveform advance pulse to the 6733 is what causes its output to
transition from one ADC channel (voltage) to another. We usually
generate this pulse from the FPGA not from a periodic clock (eg crystal
oscillator). This makes it possible to a)
