Re: [ARTIQ] Sinara clocking

2016-10-09 Thread Sébastien Bourdeauducq
On Sunday, October 09, 2016 10:20 PM, Grzegorz Kasprowicz wrote: I mean connection of HMC7043 RFSYNCIN pins. And it's HMC7044, not HMC7043. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] Sinara clocking

2016-10-09 Thread Grzegorz Kasprowicz
Which FPGA - on AMC or on RTM should generate SYSREF clock? I mean connection of HMC7043 RFSYNCIN pins. ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq

Re: [ARTIQ] Sinara clocking

2016-10-06 Thread Slichter, Daniel H. (Fed)
A few questions/comments inline below: > The crate distributes a 100MHz clock on a RTM RF backplane. This clock is > typically externally supplied from a high quality source, but it is desirable > to > include a 100MHz oscillator on the clock module for turnkey/standalone > operation (with

Re: [ARTIQ] Sinara clocking

2016-09-30 Thread Sébastien Bourdeauducq
On Friday, September 30, 2016 07:18 PM, Sébastien Bourdeauducq wrote: AD9516-1 has more coarse delay range. Scratch this. I just noticed the HMC has another "slip" mechanism that essentially gives it infinite range. So there is no reason to use the AD9516-1, other than compatibility with the

[ARTIQ] Sinara clocking

2016-09-30 Thread Sébastien Bourdeauducq
Hi, Here is a plan for clocking the Sinara system. Please comment. Crate clock distribution The crate distributes a 100MHz clock on a RTM RF backplane. This clock is typically externally supplied from a high quality source, but it is desirable to include a 100MHz