Re: Self-documenting Bit Settings

2023-08-15 Thread Dave Clark
"IBM Mainframe Assembler List" wrote on 08/15/2023 03:09:13 PM: > The technique has been described extensively by > the late Dr. John Ehrman. I think it was a Share presentation. Thanks for that. I put these comments in all three macros. MACRO TF

Re: Self-documenting Bit Settings

2023-08-15 Thread Abe Kornelis
All, The technique has been described extensively by the late Dr. John Ehrman. I think it was a Share presentation. I used to create my own version. Works like a charm. I love to be able to simply manage a bit by name, not needing to care about the label used to define the storage location.

Re: Self-documenting Bit Settings

2023-08-15 Thread Dave Clark
"IBM Mainframe Assembler List" wrote on 08/15/2023 02:07:32 PM: > Ratz! Those macros are not on my system. ;-b So, I whipped up my own simple versions and created a little test program to see how it all works. It is even compatible with my macros for conditional constructs.

Re: Self-documenting Bit Settings

2023-08-15 Thread Dave Clark
"IBM Mainframe Assembler List" wrote on 08/15/2023 04:53:03 AM: > So for example, HLASM itself has some internal macros TF, SF and > CF (test flag, set flag and clear flag) which generate code such > as the following: > > TF flag > + TM flag,L'flag Ratz! Those

Re: Self-documenting Bit Settings

2023-08-15 Thread Jon Perryman
> On Tuesday, August 15, 2023 at 02:29:07 AM PDT, Jonathan Scott > wrote: > Although it may initially seem confusing, it provides a safe way to > ensure that the named flag is mapped to the correct field: >           TF  flag > +        TM  flag,L'flag The problem is inconsistency and not

Re: Self-documenting Bit Settings

2023-08-15 Thread Jonathan Scott
Although it may initially seem confusing, the technique of defining a flag bit using EQU in the following form, using the length attribute to provide the bit mask, provides a safe way to ensure that the named flag is mapped to the correct field: flag EQU field,mask or (avoiding an