Re: the BEAR (was: New z16 Instructions)
On 4/17/2022 1:12 AM, Martin Trübner wrote: what would LBEAR do other than a LG Rn,X'110' ? Martin, X'110' is not the BEAR. The BEAR is a special register that holds the last Breaking Event Address (BEA). X'110' is simply the place where the BEAR is automatically stored when an interrupt occurs. My assumption is that STBEAR stores the BEAR into into virtual storage so the last BEA can be inspected *without* forcing an interrupt. Presumably LBEAR is a way of loading the BEAR without requiring a breaking event to do so. I can envision the usefulness of this for functions that interrupt normal instruction flow (e.g., an interrupt) and wish to restore things back the way they were (including the pre-interrupt BEAR) to maintain transparency. -- Phoenix Software International Edward E. Jaffe 831 Parkview Drive North El Segundo, CA 90245 https://www.phoenixsoftware.com/ This e-mail message, including any attachments, appended messages and the information contained therein, is for the sole use of the intended recipient(s). If you are not an intended recipient or have otherwise received this email message in error, any use, dissemination, distribution, review, storage or copying of this e-mail message and the information contained therein is strictly prohibited. If you are not an intended recipient, please contact the sender by reply e-mail and destroy all copies of this email message and do not otherwise utilize or retain this email message or any or all of the information contained therein. Although this email message and any attachments or appended messages are believed to be free of any virus or other defect that might affect any computer system into which it is received and opened, it is the responsibility of the recipient to ensure that it is virus free and no responsibility is accepted by the sender for any loss or damage arising in any way from its opening or use.
Re: Signed/unsigned operations
My guess is that there's a barrel shifter that takes on the order of a cycle regardless of the shift amount. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Paul Gilmartin [0014e0e4a59b-dmarc-requ...@listserv.uga.edu] Sent: Friday, April 15, 2022 2:59 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Signed/unsigned operations On Apr 15, 2022, at 12:47:40, Tony Harminc wrote: > > ... it's obvious that if you want > to rotate right, say 5 bits, you can instead rotate left 59 bits ... > Performance? Does the timing depend on the distance shifted? Maybe model-dependedent. How much does it matter? -- gil
Re: the BEAR (was: New z16 Instructions)
You are correct, I reversed L and ST in my thought > -Original Message- > From: IBM Mainframe Assembler List l...@listserv.uga.edu> On Behalf Of Seymour J Metz > Sent: Sunday, April 17, 2022 1:48 PM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Re: the BEAR (was: New z16 Instructions) > > Presumable LBEAR would load the actual breaking-event-address register, > not set the PSA field. > > How would STBEAR falsify the original? Were you thinking of LBEAR? > > > -- > Shmuel (Seymour J.) Metz > https://urldefense.com/v3/__http://mason.gmu.edu/*smetz3__;fg!!JmPEg > BY0HMszNaDT!r7dai4jAuwG_m8yJhCQL7ijFUUMQ2TaWGy8lb- > 5dXT5MQ5RwlutyjtWtRqv6myI15Y8QQhWaYjk7LQ$ > > > From: IBM Mainframe Assembler List [ASSEMBLER- > l...@listserv.uga.edu] on behalf of Martin Trübner [martin@PI- > SYSPROG.DE] > Sent: Sunday, April 17, 2022 4:12 AM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: the BEAR (was: New z16 Instructions) > > Dave, > > > what would LBEAR do other than a LG Rn,X'110' ? > > > and what is STBEAR good for? to falsify the original? > > > I wait for the POP to describe them in more detail > > > Martin > > Am 16.04.22 um 23:47 schrieb Gibney, Dave: > > It seems problematic to do a STBEAR, but I can see the utility of LBEAR. > Assuming the BEAR is the one I am thinking of. > > > > RDP probably not the Remote Desktop Protocol... > >
Re: the BEAR (was: New z16 Instructions)
Presumable LBEAR would load the actual breaking-event-address register, not set the PSA field. How would STBEAR falsify the original? Were you thinking of LBEAR? -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Martin Trübner [mar...@pi-sysprog.de] Sent: Sunday, April 17, 2022 4:12 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: the BEAR (was: New z16 Instructions) Dave, what would LBEAR do other than a LG Rn,X'110' ? and what is STBEAR good for? to falsify the original? I wait for the POP to describe them in more detail Martin Am 16.04.22 um 23:47 schrieb Gibney, Dave: > It seems problematic to do a STBEAR, but I can see the utility of LBEAR. > Assuming the BEAR is the one I am thinking of. > > RDP probably not the Remote Desktop Protocol... >
Re: Next instruction not needed
There is no conflict between "it can be done" and "special cases". -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Robin Vowels [robi...@dodo.com.au] Sent: Sunday, April 17, 2022 10:09 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Next instruction not needed On 2022-04-17 23:11, Seymour J Metz wrote: >> What's more, the 3 or 4 registers needed for MVCL can be loaded by a >> single instruction. > > Only in special cases. . Depends how you program the task. It can be done. . > Also, there are no cases where you need 4 > registers to fill a block. . Had you read what I wrote, you will see that I explicitly quoted 3 registers for filling a block. . > > > From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] > on behalf of Robin Vowels [robi...@dodo.com.au] > Sent: Friday, April 15, 2022 11:28 PM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Re: Next instruction not needed > > From: "Tom Harper" > Sent: Saturday, April 16, 2022 12:34 AM > Subject: Re: Next instruction needed > > >> Robin, > >> See embedded remarks. > > See mine. > > MVCL will do what you want. > It was designed to do the operation without overruns. > The lengths of the source and the destination areas are both > specified in the relevant registers, and the move terminates > when the destination area has been filled. > The true lengths of the data areas are given in registers, > and MVCL will even deal with zero lengths. > It's a dream instruction. > What's more, the 3 or 4 registers needed for MVCL can be loaded > by a single instruction. > > The most common use of MVCL is to move some text to a destination > area, and to pad that area with a given character (commonly blank, > not zero), if required. > To set an area to zeros is not something that's done frequently. > I would say, almost never. > > Your objection to MVCL needing 3 registers for your special case > (rarely needed) is specious; that 3 registers are not often available, > also specious; other instructions need 3 registers, such as MR, DR, > BXH, BXLE, and other instructions need 2 registers e,g, BCTR, > SLDA, SRDA, etc. ...
Re: Z16 principles of operation
On Apr 17, 2022, at 10:37:05, Ed Jaffe wrote: > ... > I remember once seeing the new PoOp the day before GA, but that might have > been a "fluke" due to "pilot" error. > Time zone difference? Many pubs are produced in the eastern hemisphere. -- gil
Re: Z16 principles of operation
I believe that SA22-7832-12 is the z15 edition. AFAIK the z16 edition is not yet available. Others have pointed out that the next PoOP isn't usually made available until GA of the hardware, which is said to be May 31, 2022 for z16. So it should be available in about 6 weeks, give or take a few days. Peter -Original Message- From: IBM Mainframe Assembler List On Behalf Of tom_russell tom_russell Sent: Sunday, April 17, 2022 10:26 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Z16 principles of operation Hello, I'm still missing the newest publication. I'm interested to read about the next instructions. Does someone know where to find it? Regards Yves Colliard ResourceLink has the latest - SA22-7832-12. Go to ibm.com/servers/resourcelink/svc03100.nsf You will need your IBMid. If you don't have one, you can register. Tom -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system.
Re: Z16 principles of operation
On 4/17/2022 7:25 AM, tom_russell tom_russell wrote: Hello, I'm still missing the newest publication. I'm interested to read about the next instructions. Does someone know where to find it? Regards Yves Colliard ResourceLink has the latest - SA22-7832-12. Go to ibm.com/servers/resourcelink/svc03100.nsf This is a red herring. The -12 version is for z15. As has been exhaustively stated and repeated every 18 months or so, the PoOp for a new machine does not come out until GA. I remember once seeing the new PoOp the day before GA, but that might have been a "fluke" due to "pilot" error. -- Phoenix Software International Edward E. Jaffe 831 Parkview Drive North El Segundo, CA 90245 https://www.phoenixsoftware.com/ This e-mail message, including any attachments, appended messages and the information contained therein, is for the sole use of the intended recipient(s). If you are not an intended recipient or have otherwise received this email message in error, any use, dissemination, distribution, review, storage or copying of this e-mail message and the information contained therein is strictly prohibited. If you are not an intended recipient, please contact the sender by reply e-mail and destroy all copies of this email message and do not otherwise utilize or retain this email message or any or all of the information contained therein. Although this email message and any attachments or appended messages are believed to be free of any virus or other defect that might affect any computer system into which it is received and opened, it is the responsibility of the recipient to ensure that it is virus free and no responsibility is accepted by the sender for any loss or damage arising in any way from its opening or use.
Re: the BEAR (was: New z16 Instructions)
I guess it's possibly some other BEAR. I agree that until we have a POP, I am just WAGing > -Original Message- > From: IBM Mainframe Assembler List l...@listserv.uga.edu> On Behalf Of Martin Trübner > Sent: Sunday, April 17, 2022 1:12 AM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: the BEAR (was: New z16 Instructions) > > Dave, > > > what would LBEAR do other than a LG Rn,X'110' ? > > > and what is STBEAR good for? to falsify the original? > > > I wait for the POP to describe them in more detail > > > Martin > > Am 16.04.22 um 23:47 schrieb Gibney, Dave: > > It seems problematic to do a STBEAR, but I can see the utility of LBEAR. > Assuming the BEAR is the one I am thinking of. > > > > RDP probably not the Remote Desktop Protocol... > >
Re: Next instruction not needed
- Original Message - From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> To: Sent: Saturday, April 16, 2022 1:57 PM Subject: Re: Next instruction not needed On Apr 15, 2022, at 21:30:35, Robin Vowels wrote: R0 doesn't count because no one else uses it. nonsense! (That was sarcasm.) On Apr 15, 2022, at 21:28:55, Robin Vowels wrote: MVCL will do what you want. Yes. and MVCL will even deal with zero lengths. It must, in order to deal with interruptions during padding. The most common use of MVCL is to move some text to a destination area, and to pad that area with a given character (commonly blank, not zero), if required. To set an area to zeros is not something that's done frequently. I would say, almost never. To preset storage after GETMAIN? . Might be heavy overhead for a GETMAIN of a mere 256 bytes. . But it might suffice to set counters to zero and leave buffers undefined. The length is probably a constant, but may exceed 256. I suspect MVCL is highly optimized in microcode or silicon; I could imagine special treatment of cache faults, etc. --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus
Re: Z16 principles of operation
Hello, I'm still missing the newest publication. I'm interested to read about the next instructions. Does someone know where to find it? Regards Yves Colliard ResourceLink has the latest - SA22-7832-12. Go to ibm.com/servers/resourcelink/svc03100.nsf You will need your IBMid. If you don't have one, you can register. Tom -- G. Tom Russell “Stay calm. Be brave. Wait for the signs” — Jasper FriendlyBear “… and remember to leave good news alone.” — Gracie HeavyHand
Re: Next instruction not needed
On 2022-04-17 23:11, Seymour J Metz wrote: What's more, the 3 or 4 registers needed for MVCL can be loaded by a single instruction. Only in special cases. . Depends how you program the task. It can be done. . Also, there are no cases where you need 4 registers to fill a block. . Had you read what I wrote, you will see that I explicitly quoted 3 registers for filling a block. . From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Robin Vowels [robi...@dodo.com.au] Sent: Friday, April 15, 2022 11:28 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Next instruction not needed From: "Tom Harper" Sent: Saturday, April 16, 2022 12:34 AM Subject: Re: Next instruction needed Robin, See embedded remarks. See mine. MVCL will do what you want. It was designed to do the operation without overruns. The lengths of the source and the destination areas are both specified in the relevant registers, and the move terminates when the destination area has been filled. The true lengths of the data areas are given in registers, and MVCL will even deal with zero lengths. It's a dream instruction. What's more, the 3 or 4 registers needed for MVCL can be loaded by a single instruction. The most common use of MVCL is to move some text to a destination area, and to pad that area with a given character (commonly blank, not zero), if required. To set an area to zeros is not something that's done frequently. I would say, almost never. Your objection to MVCL needing 3 registers for your special case (rarely needed) is specious; that 3 registers are not often available, also specious; other instructions need 3 registers, such as MR, DR, BXH, BXLE, and other instructions need 2 registers e,g, BCTR, SLDA, SRDA, etc. ...
Re: New z16 Instructions
---> On Sat, Apr 16, 2022 at 8:33 PM Paul Gilmartin < 0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote: > On Apr 16, 2022, at 17:32:03, Steve Smith wrote: > ... > Do any mnemonics use numeric digits? Is it IBM's intention never > to use digits in mnemonics? (But at one time IBM seemed committed > never to use mnemonics longer than four letters.) > SAM31 & its friends are all that come to mind. > > > Anyway, nothing here looks nearly as bad as the infamous introduction of > > the MSG operation. > > > I don't know that one. Did IBM step on its own toes? > I'd say it stepped on a lot of toes with that one, but not necessarily its own. It's one of 11 varieties of MULTIPLY SINGLE (13 inc. immediate forms). > > -- > gil > sas
Re: Next instruction not needed
> What's more, the 3 or 4 registers needed for MVCL can be loaded by a single > instruction. Only in special cases. Also, there are no cases where you need 4 registers to fill a block. -- Shmuel (Seymour J.) Metz http://mason.gmu.edu/~smetz3 From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf of Robin Vowels [robi...@dodo.com.au] Sent: Friday, April 15, 2022 11:28 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: Next instruction not needed From: "Tom Harper" Sent: Saturday, April 16, 2022 12:34 AM Subject: Re: Next instruction needed > Robin, > See embedded remarks. See mine. MVCL will do what you want. It was designed to do the operation without overruns. The lengths of the source and the destination areas are both specified in the relevant registers, and the move terminates when the destination area has been filled. The true lengths of the data areas are given in registers, and MVCL will even deal with zero lengths. It's a dream instruction. What's more, the 3 or 4 registers needed for MVCL can be loaded by a single instruction. The most common use of MVCL is to move some text to a destination area, and to pad that area with a given character (commonly blank, not zero), if required. To set an area to zeros is not something that's done frequently. I would say, almost never. Your objection to MVCL needing 3 registers for your special case (rarely needed) is specious; that 3 registers are not often available, also specious; other instructions need 3 registers, such as MR, DR, BXH, BXLE, and other instructions need 2 registers e,g, BCTR, SLDA, SRDA, etc. See below for interspersed replies. > Tom > On Apr 15, 2022, at 5:08 AM, Robin Vowels wrote: > > - Original Message - From: "Tom Harper" > > To: > Sent: Friday, April 15, 2022 3:06 AM > > >>> IMHO, the next instruction to add to z/Architecture would be an instruction >>> to clear storage to >>> zeros. Who needs it? I cannot recall ever seeing a program that ever did that. Nor ever needed it. >>> Right now a number of methods are in widespread use, Really? >>> none of which are clean and simple. I mean, it’s been almost sixty years. > >>> MVCL takes three registers to set up beforehand; > >> So? Write yourself a macro. Of course a macro can be written. But that’s not the point. Three registers will have to be loaded and that takes time and the registers are not always easily available. Three registers are always easily available. Think about MR, DR, BXH, BXLE, LM, etc. >> XC sets the condition code and is not variable length, and the overlapping >> MVC is a kluge > >> But it does the job well. > Except that it can only handle fixed length without an execute instruction > which is a poor > performer. There is another way to do it. >> Also needlessly sets the condition code which slows down the processor. Rubbish. >>> and not variable length either. > >> Use Ex. >A poor performer. > >>> An EX instruction is also a kluge. > >>> All you need is the address and length to accomplish this, preferably in >>> two versions, >>> one with an immediate operand for the length > >> Really?! A few lines ago, you were decrying XC and MVC because they have a >> "fixed length". >They are fixed length unless you use an execute instruction. There are other ways. >>> and another which uses, for example, a register, perhaps register zero. A >>> long displacement >>> would be a plus. > >>> To avoid issues with interruptibility, the length would need to be limited >>> to 256 bytes. > >> What? Back to a limit of 256? what's the point of that? >> MVCL will do as long as you want. > Yes it will. But a common need is for shorter lengths. > >>> I don’t think the length restriction would be an issue in most cases. > >> There's no point in having an instruction with a length restrictionof 256. > I’ve been doing this for a very long time and I will respectfully disagree > with you. > There are frequent cases to clear fields of 256 bytes or less. I disagree. The most frequent case is to move some text into a field and to blank fill the remainder of the destination area, for which MVCL is an ideal instruction. >>> Such an instruction might look like this: > >>> CLEAR FieldA > >>> Or > >>> LLGF R0,Varlen >>> CLEARR > >> A macro reference would require one require one line. > True, but not relevant. I disagree. It's precisely relevant. > The purpose of this instruction is to have a simple instruction that performs > a frequently used > function that the processor can execute quickly. I disagree that it is "a frequently used function". See above. >>> Similar instructions for compare logical and move would be nice as well. --- This email has been checked for viruses by Avast antivirus software.
Re: the BEAR (was: New z16 Instructions)
. If the POP manual is not available, where can one find the new instructions ? -- Original Message -- From: Martin Trübner To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: the BEAR (was: New z16 Instructions) Date: Sun, 17 Apr 2022 10:12:07 +0200 Dave, what would LBEAR do other than a LG Rn,X'110' ? and what is STBEAR good for? to falsify the original? I wait for the POP to describe them in more detail Martin Am 16.04.22 um 23:47 schrieb Gibney, Dave: > It seems problematic to do a STBEAR, but I can see the utility of LBEAR. > Assuming the BEAR is the one I am thinking of. > > RDP probably not the Remote Desktop Protocol... >
the BEAR (was: New z16 Instructions)
Dave, what would LBEAR do other than a LG Rn,X'110' ? and what is STBEAR good for? to falsify the original? I wait for the POP to describe them in more detail Martin Am 16.04.22 um 23:47 schrieb Gibney, Dave: It seems problematic to do a STBEAR, but I can see the utility of LBEAR. Assuming the BEAR is the one I am thinking of. RDP probably not the Remote Desktop Protocol...
