... and CPUs with this feature might be cheaper
..or they may be faster, if storage key checking imposes memory access
overheads?
On 7/06/2022 5:26 pm, dave.g4...@gmail.com wrote:
-Original Message-
From: IBM Mainframe Assembler List On Behalf Of Bob Raicer
Sent: 07 June 2022
@Ed's approach is elegant, although a maintenance newbie might have trouble understanding what
256AL1(*-TABLE) did.
Ed’s technique is standard practice here for building such a table.
As for newbies who may be unclear about the machine code that this generates:
“Use the listing, Luke, use the
IPM R0 SAVE COND CODE, PROGRAM MASK
STR0,IXWKPMSKSAVE COND CODE, PROGRAM MASK
..
..
L R0,IXWKPMSKGET COND CODE, PROGRAM MASK
SPM R0 SET COND CODE, PROGRAM MASK
On 5/05/2018 8:22 PM,
I did not know John personally, only through his many posts to this site
and his wider contributions to HLASM.
It's fair to say his was a meaningful life, and that he made a
difference to many people and to many enterprises.
He was unfailingly respectful of others, a valuable counterweight in
Milena, please accept condolences from me. I knew your father only
through his online posts. Passionate and diligent, at times to the
point of single-mindedness, he'll be missed both here and in other
fora for the extensive and valuable assistance he gave over many years.
Vale Chris.
Graeme
Yeah, I always found that assigning object- or task- oriented names
to registers was a recipe for disaster; You inevitably end up with
multiple names for the same resource (eg: RSRCE EQU 7 and R7 EQU 7)
and nothing stops you, or a later programmer, inadvertantly selecting
by its rn name a
