Re: Decimal Floating Point Numbers

2024-03-07 Thread John Dravnieks
the quantum of a value. While the Quantize instruction adjusts the quantum - this might be used where the value is say a balance in dollars and you just want to keep 2 digits to the right of the decimal point. Kind regards John Dravnieks

Re: SV: ASMA057E Undefined operation code SR 15,15

2023-11-15 Thread John Dravnieks
' This little snippet will work as expected while this will not SETC 'label SR 15,15' Kind regards John Dravnieks (former HLASM developer)

Re: Self-documenting Bit Settings

2023-08-16 Thread John Dravnieks
https://bitsavers.org/pdf/ibm/share/Ehrman_-_Assembler_Language_as_a_Higher_Level_Language_SHARE_Summer_2002.pdf This is the presentation that Abe is referring to. Kind regards John

TBEGINC question

2021-01-28 Thread John Dravnieks
5 tbeginc 0,0 000FFE 0610 6 bctr 1,0 001000 5010 D0000 7 st1,0(,13) 001004 B2F8 8 TEND Kind Regards John Dravnieks, 21st Century Software

Re: HLASM anomaly

2017-02-28 Thread John Dravnieks
' or TMLL 1,1+2+4+8+16+32+64+128 - exactly the same object code - again which is easier to understand from the source? Kind Regards John Dravnieks

Re: HLASM anomaly

2017-02-23 Thread John Dravnieks
Fellow listers I used to develop and maintain HLASM and there were lots of internal discussions about how to handle items like 16 bit immediate opearnds. One point is that internally the assembler has an expression processor for instruction operands, and it has another one for DC operands -

Re: curious: MVHI vs XC to "zero" a halfword.

2017-01-12 Thread John Dravnieks
There is always some method in the instructions. All Load Logical instructions update the part of the register as asked for, and then zero the rest of the first operand (for example LLC - load logical character loads the low order byte from the second operand and zeroes

Re: SIIS "issue" after upgrade to z13 machine.

2016-11-13 Thread John Dravnieks
Hello Philippe A comment about replacing LTR/BZ combinations with CIJE - the compare immediate instructions do NOT set the condition code so you need to make sure that the BZ is the only instruction testing the condition code. Also earlier, you made a comment about Execute that you need to

Re: Friday puzzle: CNOP 1,2

2016-08-22 Thread John Dravnieks
ubject:Re: Friday puzzle: CNOP 1,2 Sent by:IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> Won't this possibly overlay the previous field if the ORG happens to land on a half-word boundary? Maybe a set of ORGs: ORG *+1 ORG *,2,-1 Tony Thigpen Jo

Re: Friday puzzle: CNOP 1,2

2016-08-22 Thread John Dravnieks
Why not use ORG to do this for you? ORG *,2,-1take current position (*), align to 2 byte boundary (if required), and move back one byte Kind Regards John R Dravnieks From: "Ngan, Robert" To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Date:

Re: load logical halfword immediate

2016-01-20 Thread John Dravnieks
LLHRL ? Kind Regards John R Dravnieks Internet: dr...@au.ibm.com From: "Swarbrick, Frank" To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Date: 21/01/2016 03:25 Subject:load logical halfword immediate Sent by:IBM Mainframe Assembler List

Re: load logical halfword immediate

2016-01-20 Thread John Dravnieks
Oops - close not quite what the user ordered. LLHRL still addresses an area in storage for the halfword data. Kind Regards John R Dravnieks From: John Dravnieks/Australia/IBM@IBMAU To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Date: 21/01/2016 14:38 Subject:Re: load logical

Re: MultiTasking question

2013-11-26 Thread John Dravnieks
Why not use the EVENTS macro to handle the list of ECBs? I think that it provides the same functionality, perhaps in a slightly different form. Kind Regards John R Dravnieks From: Blaicher, Christopher Y. cblaic...@syncsort.com To: ASSEMBLER-LIST@listserv.uga.edu, Date: 27/11/2013

Re: the fun of coding in HLASM

2012-11-15 Thread John Dravnieks
To make things more readable, then I would recommend using LOCTR. Define one location counter for the code, and another one for the data areas a csect static loctr , You will need to set up addressability to this area code loctr . . . clc chk_string,0(r6) static

Re: Strange PC entry

2012-08-23 Thread John Dravnieks
And the other effect of having a PC section first is that any generated DCs from the implicit LTORG done as part of the END statement processing will be also be in that first section. Often a cause of addressability errors to literals. Regards John

zEnterprise - new opcodes

2010-08-26 Thread John Dravnieks
The mnemonics for LOAD ON CONDITION and STORE ON CONDITION (and their extended friends) will be changed by PK87960 as follows Original New Extended - LGOC LOCG LOCGELOCGHLOCGL LOCGNE LOCGNH

Re: zEnterprise - new PoPS?

2010-08-05 Thread John Dravnieks
Abe You are correct - LGROCNE is the intended mnemonic and the APAR text has been edited to correct this typo. Kind Regards John R Dravnieks From: Abe Kornelis a...@bixoft.nl To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Date: 04/08/2010 19:07 Subject:Re: zEnterprise - new PoPS? Sent