Indeed... one of the few omissions of the z/Architecture instruction set is
the lack of LLI* instructions that operate only on the traditional 32-bit
registers.  Seems to me they probably should have been named LLGI* to be
consistent.


sas


On Fri, Jan 13, 2017 at 1:40 AM, John Dravnieks <dr...@au1.ibm.com> wrote:

> There is always some method in the instructions.
>
> All Load Logical instructions update the part of the register as asked
> for, and then zero the rest of the first operand
>                          (for example LLC - load logical character loads
> the low order byte from the second operand and zeroes the rest of the
> register)
> All Insert Immediate instructions update the part of the register as asked
> for  - the rest of the first operand is left as is
>                         (for example, IILL   -  the much older IC could be
> considered as an Insert Immediate Character)
> All Load instructions sign extend the second operand if required and use
> that result to update the first operand.
>                         (for example, LB - Load Byte - sign extends the
> one byte second operand and updates the register with the result
>
> Kind Regards
>
> John
>
> Internet: dr...@au.ibm.com
>
>
>
> From:   Charles Mills <charl...@mcn.org>
> To:     ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Date:   13/01/2017 10:45
> Subject:        Re: curious: MVHI vs XC to "zero" a halfword.
> Sent by:        IBM Mainframe Assembler List
> <ASSEMBLER-LIST@LISTSERV.UGA.EDU>
>
>
>
> Noooooooooooooooooo!
>
> What do a senior z/OS developer and I have in common? We both got our
> butts bitten by this!
>
> LLILF: "The second operand is placed in bit positions of the first
> operand. The remainder of the first operand is set to zeros."
>
> Charles
>
> -----Original Message-----
> From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU
> ] On Behalf Of Blaicher, Christopher Y.
> Sent: Thursday, January 12, 2017 6:34 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: curious: MVHI vs XC to "zero" a halfword.
>
> Sorry, LLILF only load bits 32 to 63, not 0 to 63. So, LLILF meets your
> requirement to load only 32 bits/
>



-- 
sas

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