Re: Source address significance for clearing MVCL

2017-08-17 Thread Gary Freestone
Yes, I do believe you are correct. Checked a bit of old code for clearing an area and both source addr and length are 0 Regards, Gary Freestone -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Charles Mills Sent: Thursday, 17

Would like your opinion before reporting problem

2017-08-23 Thread Gary Freestone
).DDOK And all works fine. Comments ? Do you think it should work ? (Does it for you)? Regards, Gary Freestone.

BPXWDYN - Bug or no bug ?

2018-02-19 Thread Gary Freestone
Problem is because I'm not getting a new allocation my FREE is freeing up a DDNAME allocated by a totally different process. In my case causing an abend sometime later because a DDname that should be allocated is not. This doesn't seem right to me. An "ALLOC" should do a new allocation every time. Comments Gary Freestone

Re: BPXWDYN - Bug or no bug ?

2018-02-19 Thread Gary Freestone
Sorry guys. Wrong forum. Apologies. Gary Freestone -Original Message- From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Gary Freestone Sent: Tuesday, 20 February 2018 12:04 AM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: BPXWDYN - Bug or no bug

Using both ends of a register

2019-02-12 Thread Gary Freestone
Hello, Is there an assembler instruction that that moves the lower 32 bits of a register to the high end of an register and visa versa. The closest I’ve found is LOCFHR but it has some CC processing involved. I’m finding the POP so big to thumb through these days ☹ Regards

Re: Using both ends of a register

2019-02-12 Thread Gary Freestone
Thanks all, I didn't expect to look "in the R's" for a load instruction. Interestingly, I was looking at an old presentation last week that included the RNSBG, RXSBG, RISGB and ROSBG instructions. It seems I was closer than I thought. Regards, Gary >LHLR R1,R2 is the "perfect" match, and