Re: [PATCH 3/4] ath10k: Enable SRRI/DRRI support on ddr for WCN3990

[Kalle Valo]

pill...@codeaurora.org writes:

> From: Govind Singh 
>
> SRRI/DRRI are not mapped in the HW Shadow block and can lead
> to un-clocked access if common subsystem in the target is
> powered down due to idle mode.
>
> To mitigate this problem SRRI/DRRI can be read from
> DDR instead of doing an actual hardware read.
> Host allocates non cached memory on ddr and configures
> the physical address of this memory to the CE hardware.
> The hardware updates the RRI on this particular location.
> Read SRRI/DRRI from DDR location instead of
> direct target read.
>
> Enable retention restore on ddr using hw params to enable
> in specific targets.
>
> Signed-off-by: Govind Singh 
> Signed-off-by: Rakesh Pillai 

[...]

> + for (i = 0; i < CE_COUNT; i++) {
> + ctrl1_regs = ar->hw_ce_regs->ctrl1_regs->addr;
> + ce_base_addr = ath10k_ce_base_address(ar, i);
> + ath10k_ce_write32(ar, ce_base_addr + ctrl1_regs,
> +   ath10k_ce_read32(ar,
> +   ce_base_addr + ctrl1_regs) |
> +   ar->hw_ce_regs->upd->mask);
> + }

This gives a checkpatch warning:

drivers/net/wireless/ath/ath10k/ce.c:1917: Alignment should match open 
parenthesis

You could fix that, and make the code a lot more readable, with
something like this:

tmp = ath10k_ce_read32(ar, ce_base_addr + ctrl1_regs);
tmp |= ar->hw_ce_regs->upd->mask;
ath10k_ce_write32(ar, ce_base_addr + ctrl1_regs, tmp);

Usually it's a good practise avoid making clever tricks, simple code is
a lot easier to read.

-- 
Kalle Valo

___
ath10k mailing list
ath10k@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/ath10k

[PATCH 3/4] ath10k: Enable SRRI/DRRI support on ddr for WCN3990

[pillair]

From: Govind Singh 

SRRI/DRRI are not mapped in the HW Shadow block and can lead
to un-clocked access if common subsystem in the target is
powered down due to idle mode.

To mitigate this problem SRRI/DRRI can be read from
DDR instead of doing an actual hardware read.
Host allocates non cached memory on ddr and configures
the physical address of this memory to the CE hardware.
The hardware updates the RRI on this particular location.
Read SRRI/DRRI from DDR location instead of
direct target read.

Enable retention restore on ddr using hw params to enable
in specific targets.

Signed-off-by: Govind Singh 
Signed-off-by: Rakesh Pillai 
---
 drivers/net/wireless/ath/ath10k/ce.c   | 102 +++--
 drivers/net/wireless/ath/ath10k/ce.h   |  10 
 drivers/net/wireless/ath/ath10k/core.c |  13 +
 drivers/net/wireless/ath/ath10k/hw.c   |   9 ++-
 drivers/net/wireless/ath/ath10k/hw.h   |  13 -
 drivers/net/wireless/ath/ath10k/snoc.c |   3 +
 6 files changed, 141 insertions(+), 9 deletions(-)

diff --git a/drivers/net/wireless/ath/ath10k/ce.c 
b/drivers/net/wireless/ath/ath10k/ce.c
index 5053dd92bf01..b21fbedd0cad 100644
--- a/drivers/net/wireless/ath/ath10k/ce.c
+++ b/drivers/net/wireless/ath/ath10k/ce.c
@@ -185,11 +185,30 @@ static inline u32 
ath10k_ce_src_ring_write_index_get(struct ath10k *ar,
ar->hw_ce_regs->sr_wr_index_addr);
 }
 
+static inline u32 ath10k_ce_src_ring_read_index_from_ddr(struct ath10k *ar,
+u32 ce_id)
+{
+   struct ath10k_ce *ce = ath10k_ce_priv(ar);
+
+   return ce->vaddr_rri[ce_id] & CE_DDR_RRI_MASK;
+}
+
 static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,
u32 ce_ctrl_addr)
 {
-   return ath10k_ce_read32(ar, ce_ctrl_addr +
-   ar->hw_ce_regs->current_srri_addr);
+   struct ath10k_ce *ce = ath10k_ce_priv(ar);
+   u32 ce_id = COPY_ENGINE_ID(ce_ctrl_addr);
+   struct ath10k_ce_pipe *ce_state = >ce_states[ce_id];
+   u32 index;
+
+   if (ar->hw_params.rri_on_ddr &&
+   (ce_state->attr_flags & CE_ATTR_DIS_INTR))
+   index = ath10k_ce_src_ring_read_index_from_ddr(ar, ce_id);
+   else
+   index = ath10k_ce_read32(ar, ce_ctrl_addr +
+ar->hw_ce_regs->current_srri_addr);
+
+   return index;
 }
 
 static inline void
@@ -266,11 +285,31 @@ static inline void 
ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
  ath10k_set_ring_byte(n, ctrl_regs->dst_ring));
 }
 
+static inline
+   u32 ath10k_ce_dest_ring_read_index_from_ddr(struct ath10k *ar, u32 
ce_id)
+{
+   struct ath10k_ce *ce = ath10k_ce_priv(ar);
+
+   return (ce->vaddr_rri[ce_id] >> CE_DDR_DRRI_SHIFT) &
+   CE_DDR_RRI_MASK;
+}
+
 static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,
 u32 ce_ctrl_addr)
 {
-   return ath10k_ce_read32(ar, ce_ctrl_addr +
-   ar->hw_ce_regs->current_drri_addr);
+   struct ath10k_ce *ce = ath10k_ce_priv(ar);
+   u32 ce_id = COPY_ENGINE_ID(ce_ctrl_addr);
+   struct ath10k_ce_pipe *ce_state = >ce_states[ce_id];
+   u32 index;
+
+   if (ar->hw_params.rri_on_ddr &&
+   (ce_state->attr_flags & CE_ATTR_DIS_INTR))
+   index = ath10k_ce_dest_ring_read_index_from_ddr(ar, ce_id);
+   else
+   index = ath10k_ce_read32(ar, ce_ctrl_addr +
+ar->hw_ce_regs->current_drri_addr);
+
+   return index;
 }
 
 static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,
@@ -486,7 +525,7 @@ static int _ath10k_ce_send_nolock_64(struct ath10k_ce_pipe 
*ce_state,
struct ath10k_ce_ring *src_ring = ce_state->src_ring;
struct ce_desc_64 *desc, sdesc;
unsigned int nentries_mask = src_ring->nentries_mask;
-   unsigned int sw_index = src_ring->sw_index;
+   unsigned int sw_index;
unsigned int write_index = src_ring->write_index;
u32 ctrl_addr = ce_state->ctrl_addr;
__le32 *addr;
@@ -500,6 +539,11 @@ static int _ath10k_ce_send_nolock_64(struct ath10k_ce_pipe 
*ce_state,
ath10k_warn(ar, "%s: send more we can (nbytes: %d, max: %d)\n",
__func__, nbytes, ce_state->src_sz_max);
 
+   if (ar->hw_params.rri_on_ddr)
+   sw_index = ath10k_ce_src_ring_read_index_from_ddr(ar, 
ce_state->id);
+   else
+   sw_index = src_ring->sw_index;
+
if (unlikely(CE_RING_DELTA(nentries_mask,
   write_index, sw_index - 1) <= 0)) {
ret = -ENOSR;
@@ -1016,7 +1060,10 @@ int ath10k_ce_completed_send_next_nolock(struct 
ath10k_ce_pipe