[PATCH 1/3] scripts: use #!/usr/bin/env bash shebang instead of #!/bin/bash

Some distributions might not have bash in /bin, but in $PATH. Using #!/usr/bin/env bash solves this, and is consistent with how the perl and python shebangs look like in the tree. --- scripts/canon-a1100-image| 2 +- scripts/check_size | 2 +- scripts/dfuboot.sh

[PATCH 2/3] dts/scripts: use #!/usr/bin/env bash shebang instead of #!/bin/bash

Some distributions might not have bash in /bin, but in $PATH. Using #!/usr/bin/env bash solves this, and is consistent with how the perl and python shebangs look like in the tree. --- dts/scripts/cronjob | 2 +- dts/scripts/index-filter.sh | 2 +- dts/scripts/merge-new-release.s

use /usr/bin/env bash shebang instead of /bin/bash

Some distributions might not have bash in /bin, but in $PATH. Using #!/usr/bin/env bash solves this, and is consistent with how the perl and python shebangs look like in the tree. ___ barebox mailing list barebox@lists.infradead.org http://lists.inf

[PATCH 3/3] docs: use #!/usr/bin/env bash shebang instead of #!/bin/bash

Some distributions might not have bash in /bin, but in $PATH. Using #!/usr/bin/env bash solves this, and is consistent with how the perl and python shebangs look like in the tree. --- Documentation/user/usb.rst | 2 +- MAKEALL| 2 +- 2 files changed, 2 insertions(+), 2 deletio

Re: [PATCH] MIPS: Makefile: minor codingstyle fix

On Wed, Nov 27, 2019 at 09:07:51AM +0800, Du Huanpeng wrote: > it exceeds 80 chararacters per line, but is more readable and > agrees agrees with the previous lines. > > Signed-off-by: Du Huanpeng > --- > arch/mips/Makefile | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) Applied, tha

Re: macro about loongson's CPU & SoC

On Tue, Nov 26, 2019 at 09:03:58PM +0800, Du Huanpeng wrote: > > The name CPU_LOONGSON1B is used in the linux kernel. > > Please keep barebox macro name in sync with linux kernel. > shall we use the rules in a "balanced" way? :) > > the name CPU_LOONGSON1B is used in the kernel, it is true. > if y

Re: [PATCH 1/2] pstore: fix build by re-resolving botched merge conflict

On Tue, Nov 26, 2019 at 11:56:59AM +0100, Ahmad Fatoum wrote: > 297ac7288 ("pstore: Only capture log messages") removed the pstore console. > v3 of the eventually merged 75a74b5c ("console: fix out-of-bounds read > in dputc(/dev/*, ...)") reinstated part of this code, which broke the > pstore build

Re: [PATCH 3/4] of/gpio: Support gpio-line-names property

On Wed, Nov 27, 2019 at 01:35:21PM +0100, Ahmad Fatoum wrote: > Hello Sascha, > > On 11/27/19 1:32 PM, Sascha Hauer wrote: > > barebox contains functions and commands to change and delete properties > > and nodes. We shouldn't store pointers into the live tree anywhere. > > aren't these fixups do

Re: [PATCH 3/4] of/gpio: Support gpio-line-names property

Hello Sascha, On 11/27/19 1:32 PM, Sascha Hauer wrote: > barebox contains functions and commands to change and delete properties > and nodes. We shouldn't store pointers into the live tree anywhere. aren't these fixups done just before boot? What users change the live device tree? -- Pengutroni

Re: [PATCH 3/4] of/gpio: Support gpio-line-names property

On Wed, Nov 27, 2019 at 12:31:37PM +0100, Ahmad Fatoum wrote: > Hello Sascha, > > On 11/27/19 12:16 PM, Sascha Hauer wrote: > > GPIOs can be given names with the gpio-line-names device tree property. > > This patch adds support for it. > > > > Signed-off-by: Sascha Hauer > > --- > > drivers/gpi

[PATCH] ARM64: Switch to 4 level page tables

3 level page tables only allow to resolve 39 bit addresses. Switch to 4 level page tables to add support for bigger physical address ranges. This is needed for example on Layerscape SoCs where the PCI windows are outside the 39bit range. The early MMU support still uses 39bit addressing. We only u

Re: [PATCH 3/4] of/gpio: Support gpio-line-names property

Hello Sascha, On 11/27/19 12:16 PM, Sascha Hauer wrote: > GPIOs can be given names with the gpio-line-names device tree property. > This patch adds support for it. > > Signed-off-by: Sascha Hauer > --- > drivers/gpio/gpiolib.c | 16 +++- > 1 file changed, 15 insertions(+), 1 deletio

[PATCH 3/6] ARM Layerscape: ls1046ardb: Fix SPI NOR flash compatibles

The upstream dts file has a "spansion,m25p80" as compatible string for the SPI NOR flashes. This doesn't match the real chip which identifies itself as "s25fl512s". The driver warns about this. Change the compatible to "jedec,spi-nor" to avoid such issues. Signed-off-by: Sascha Hauer --- arch/ar

[PATCH 5/6] ARM Layerscape: ls1046ardb: Fix EEPROM nodes

The ls1046ardb only has one EEPROM instead of two and this is a 24c04 (which spans two addresses on the I2C bus) and not a 24c512. Signed-off-by: Sascha Hauer --- arch/arm/dts/fsl-ls1046a-rdb.dts | 15 +++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dt

[PATCH 4/6] ARM Layerscape: ls1046ardb: Enable PCIe support

Enable the PCIe nodes on the ls1046ardb board. U-Boot registers the PCIe devices based on the SERDES configuration, but for us it's easier to just enable them in the device tree. Signed-off-by: Sascha Hauer --- arch/arm/dts/fsl-ls1046a-rdb.dts | 14 ++ 1 file changed, 14 insertions(+

[PATCH 2/6] ARM Layerscape: ls1046ardb: Add barebox update handler

Add a barebox update handler for easy barebox update. Signed-off-by: Sascha Hauer --- arch/arm/boards/ls1046ardb/board.c | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boards/ls1046ardb/board.c b/arch/arm/boards/ls1046ardb/board.c index 0846df9fad..606f65ce9d 100644 --- a/arc

[PATCH] ARM: Layerscape: TQMLS1046a: Fix partition name

The barebox partition on the SD card starts at offset 0x1000, so the partition node should be named partition@1000. Signed-off-by: Sascha Hauer --- arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.

[PATCH 6/6] ARM Layerscape: ls1046ardb: read nxid eeprom

This adds support for reading the EEPROM which has a "NXID" data structure on it. The MAC addresses for the ethernet devices are found here which are registered with this patch. The NXID data structure is also found on other NXP Layerscape boards, so once we support other boards the code should be

[PATCH 1/6] ARM Layerscape: ls1046ardb: Fix SD partitions

barebox and its environment should be in the first MiB of the SD card. With this we won't overwrite any partitions from the partition table. While at it add a barebox partition for a future update handler. Signed-off-by: Sascha Hauer --- arch/arm/dts/fsl-ls1046a-rdb.dts | 9 +++-- 1 file cha

[PATCH 0/6] Layerscape ls1046ardb update

Some updates for the Layerscape ls1046ardb board. Sascha Hauer (6): ARM Layerscape: ls1046ardb: Fix SD partitions ARM Layerscape: ls1046ardb: Add barebox update handler ARM Layerscape: ls1046ardb: Fix SPI NOR flash compatibles ARM Layerscape: ls1046ardb: Enable PCIe support ARM Layerscap

[PATCH 11/12] PCI: dwc: Return directly when num-lanes is not found

Port of Linux commit 66de33f09fd97201847de7e1e2ec8a117242e1d6 The num-lanes is optional since it is not needed on some platforms that bring up the link in firmware. The link programming is based on the num-lanes properties (which is optional); if it is not present code must return

[PATCH 07/12] PCI: dwc: imx6: Share PHY debug register definitions

Port of Linux commit 60ef4b072ba089440531287f72740d94ed1e8dd1 Both pcie-designware.c and pci-imx6.c contain custom definitions for PHY debug registers R0/R1 and on top of that there's already a definition for R0 in pcie-designware.h. Move all of the definitions to pcie-designware.h

[PATCH 12/12] PCI: Add layerscape PCIe driver

This adds support for the designware based PCIe controller found on Layerscape SoCs. The driver is based on Linux-5.4. The device tree fixups have been taken from U-Boot 2019.10. Signed-off-by: Sascha Hauer --- arch/arm/Kconfig | 1 + drivers/pci/Kconfig | 7 + drivers/p

[PATCH 05/12] PCI: dwc: Enable iATU unroll for endpoint too

Port of Linux commit a9f4c2d2f99ec85ebc734a5bfb21a2cf93c169ad iatu_unroll_enabled flag is set only for Designware in host mode. However iATU unroll can be applicable for endpoint mode too. Set iatu_unroll_enabled flag in dw_pcie_setup() which is common for both host mode and endpo

[PATCH 04/12] PCI: dwc: Make use of BIT() in constant definitions

Port of Linux commit 0e11faa48b07a063289d65363015a3d51ca4c337 Avoid using explicit left shifts and convert various definitions to use BIT() instead. No functional change intended. Signed-off-by: Andrey Smirnov [lorenzo.pieral...@arm.com: fixed PORT_LOGIC_SPEED_CHANGE redefinition

[PATCH 06/12] PCI: dwc: Fix ATU identification for designware version >= 4.80

Port of Linux commit 2aadcb0cd39198833fabe1c45084f78686e71a6c Synopsys designware version >= 4.80 uses a separate register space for programming ATU. The current code identifies if there exists a separate register space by accessing the register address of ATUs in designware versio

[PATCH 09/12] PCI: dwc: rename readl/writel_dbi ops to read/write_dbi

struct dw_pcie_ops read/writel_dbi functions can read values of any size, so with readl/writel they are misnamed. Rename them to read/write which also matches the kernel driver. Signed-off-by: Sascha Hauer --- drivers/pci/pcie-designware.c | 16 drivers/pci/pcie-designware.h |

[PATCH 01/12] PCI: dwc: Don't hard-code DBI/ATU offset

Port of Linux commit 6d6b05e3d5337f645a411cdf72f1a083e495acb8 The DWC PCIe core contains various separate register spaces: DBI, DBI2, ATU, DMA, etc. The relationship between the addresses of these register spaces is entirely determined by the implementation of the IP block, not by

[PATCH 10/12] PCI: dwc: Sync register definitions with Linux-5.4

Update the dwc register definitions with Linux-5.4 to make further syncinf with the Linux driver easier. Signed-off-by: Sascha Hauer --- drivers/pci/pcie-designware.h | 85 +-- 1 file changed, 51 insertions(+), 34 deletions(-) diff --git a/drivers/pci/pcie-design

[PATCH 08/12] PCI: dwc: Cleanup DBI,ATU read and write APIs

Port of Linux commit 7bc082d7e97009f252bd432de5d476b0bcf3b266 Cleanup DBI read and write APIs by removing leading "__" (underscore) from their names as there is no reason to have leading underscores in the first place in the function definition. Remove dbi/dbi2 base address parame

[PATCH 03/12] PCI: dwc: Add dw_pcie_disable_atu()

This adds dw_pcie_disable_atu() taken from Linux-5.4. This is needed by the upcoming Layerscape driver. Signed-off-by: Sascha Hauer --- drivers/pci/pcie-designware.c | 20 drivers/pci/pcie-designware.h | 8 2 files changed, 28 insertions(+) diff --git a/drivers/pc

[PATCH 02/12] PCI: dwc: Make use of IS_ALIGNED()

Port of Linux commit 4f8bbd2f8e7c4f3112506bf7362aed3a5495d51b Make the intent a bit more clear as well as get rid of explicit arithmetic by using IS_ALIGNED() to determine if "addr" is aligned to "size". No functional change intended. Signed-off-by: Andrey Smirnov Signed-off-

[PATCH 00/12] Designware PCIe updates and Layerscape support

s series has some updates to the Designware PCIe controller driver taken from Linux and finally adds support for the Layerscape incarnation of the Designware PCIe core. Sascha Hauer (12): PCI: dwc: Don't hard-code DBI/ATU offset PCI: dwc: Make use of IS_ALIGNED() PCI: dwc: Add dw_pcie_disabl

[PATCH 0/4] support for gpio-line-names

Linux supports the device tree property "gpio-line-names" which allows it name GPIOs from the device tree. This adds support for this property to barebox as well. With this the gpio commands not only accept a GPIO label (which is given by the requester of the GPIO), but also a GPIO name. Sascha Ha

[PATCH 3/4] of/gpio: Support gpio-line-names property

GPIOs can be given names with the gpio-line-names device tree property. This patch adds support for it. Signed-off-by: Sascha Hauer --- drivers/gpio/gpiolib.c | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c inde

[PATCH 1/4] of: Add of_property_read_string_array()

of_property_read_string_array() is used to read a multistring device tree property into an array of strings. This is taken from the kernel. It is implemented around of_property_read_string_helper() which can be used to implement of_property_count_strings() and of_property_read_string_index() as wel

[PATCH 2/4] gpio: Introduce GPIO names

This introduces GPIO names. So far we only have labels which are given by the requester. In contrast names are given by the provider and do not change depending on whoever requests a GPIO. The gpio commands now also accept to reference a GPIO by name. The printing of the gpioinfo command is adjuste

[PATCH 4/4] ARM: Layerscape: TQMLS1046a: Add gpio-line-names

The GPIO line names are taken from https://github.com/tq-systems/u-boot-tqmaxx/blob/warrior.TQMLS1046A.BSP.SW.0003/board/tqc/common/tqc_mbls10xxa.c Signed-off-by: Sascha Hauer --- arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts | 48 +++ 1 file changed, 48 insertions(+) diff --git