[PATCH 04/21] MIPS: barebox.lds: remove extra whitespace

Signed-off-by: Denis Orlov --- arch/mips/lib/barebox.lds.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/mips/lib/barebox.lds.S b/arch/mips/lib/barebox.lds.S index 1259a4e94f..0720f9295d 100644 --- a/arch/mips/lib/barebox.lds.S +++ b/arch/mips/lib/barebox.lds.S @@ -3,7 +3,6 @@ *

[PATCH 19/21] MIPS: c-r4k: do flush secondary cache

Even though we probe for the secondary cache, we don't actually utilize it when flushing. It seems that the reason for this is that no MIPS board currently supported in barebox actually has secondary caches and thus requires the additional logic in handling them. Add the required functions and

[PATCH 20/21] MIPS: c-r4k: remove extra function declaration

'r4k_cache_init()' is already declared in the appropriate 'asm/cache.h' header. Signed-off-by: Denis Orlov --- arch/mips/lib/c-r4k.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c index 2fb4e90138..44cf57d99b 100644 --- a/arch/mips/lib/c-r4k.c

[PATCH 17/21] MIPS: c-r4k: prettify code in __BUILD_BLAST_CACHE_RANGE

Even though the original code was taken from Linux, it is quite old and crufty. Replace the 'while (1)' loop with the 'for' one, use const for constant variables and use ALIGN_DOWN macro instead of repeating its code. Signed-off-by: Denis Orlov --- arch/mips/lib/c-r4k.c | 13 + 1

[PATCH 21/21] MIPS: reloc: use IS_ALIGNED macro to check for an alignment

Improves the code readability a tiny little bit. Signed-off-by: Denis Orlov --- arch/mips/lib/reloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c index 83b4040d95..a9078aa813 100644 --- a/arch/mips/lib/reloc.c +++

[PATCH 16/21] MIPS: main_entry: remove exception vector array

This code must have been taken from Linux, where such a mechanism allows for an efficient exception vector replacement for board-specific code. We don't really need that. If some extensions for exception vector are to be required, this may be done inside the generic handler code anyway. As we are

[PATCH 18/21] MIPS: c-r4k: generate blast_*cache functions via macros

This gets us rid of this logic repeated in 'flush_cache_all()' for each cache and allows to use blast_*cache funcs elsewhere if such a need arises. Signed-off-by: Denis Orlov --- arch/mips/lib/c-r4k.c | 41 - 1 file changed, 24 insertions(+), 17

[PATCH 01/21] MIPS: addrspace: rectify ksseg segment naming

There was a slight confusion in macro definitions for various memory segments. In the 64-bit mode, there was CKSEG2ADDR defined without a corresponding CKSEG2 definition, which led to errors when trying to actually use it. Instead there was a CKSSEG definition that stands for exactly the same

[PATCH 03/21] MIPS: main_entry-pbl: remove unused variable

For some reason we do set 'ttb' global variable, however we never end up using it. Signed-off-by: Denis Orlov --- arch/mips/boot/main_entry-pbl.c | 4 1 file changed, 4 deletions(-) diff --git a/arch/mips/boot/main_entry-pbl.c b/arch/mips/boot/main_entry-pbl.c index f75ec03851..78982fd995

[PATCH 14/21] MIPS: clean up barebox proper entry point

For MIPS, we don't actually have boards which lack PBL in the resulting image. As such, the code in _start() is mostly redundant: the stack was setup in ENTRY_FUNCTION_END, while copying the code to the link location is not needed - it should already be executing at TEXT_BASE, where we have

[PATCH 13/21] MIPS: pbl: do enable 64-bit addressing in PBL

It seems more reasonable to do that in PBL code that initializes all the other appropriate CP0 register bits. This also makes a corresponding call in barebox proper entry code redundant, paving the way to its removal. Signed-off-by: Denis Orlov --- arch/mips/include/asm/pbl_macros.h | 1 + 1

[PATCH 15/21] MIPS: main_entry: properly set XTLB handler for 64-bit mode

The offset of the TLB Load exception is different when 64-bit addressing is enabled - 0x80 is used instead of 0x0. To simplify things, just copy the handler code twice, for each of the cases. While at it, also remove the incomprehensible cpu_has_4kex check. All of the supported CPUs have MIPS R4K

[PATCH 09/21] MIPS: pbl_macros: use .asciiz instead of .ascii + .byte 0

GAS allows to use '.asciz'/'.asciiz' instead of manually writing '.byte 0' to null-terminate the string specified in '.ascii' directive. Do just that in 'mips_barebox_10h'. The malta-specific entry code currently does the same. Signed-off-by: Denis Orlov --- arch/mips/include/asm/pbl_macros.h |

[PATCH 11/21] MIPS: pbl: put mips_barebox_10h into ENTRY_FUNCTION

Remove duplicated macro calls by moving it into a common macro, as is done in ARM code. Some boards were missing this one for no good reason, it seems. Well, now they don't. Signed-off-by: Denis Orlov --- arch/mips/boards/8devices-lima/lowlevel.S | 2 --

[PATCH 10/21] MIPS: malta: remove duplicated barebox magic code

Use 'mips_barebox_10h' macro instead. Remove the comment about the same address being reserved for a Board ID as we don't really do anything about it anyway. Signed-off-by: Denis Orlov --- arch/mips/boards/qemu-malta/lowlevel.S | 11 +-- 1 file changed, 1 insertion(+), 10 deletions(-)

[PATCH 08/21] MIPS: malta: merge GT64120 headers

The various definitions related to GT64120 system controller were split between two headers: 'asm/gt64120.h' and 'mach/mach-gt64120.h'. It seems that they were taken from Linux in this form. No reason to keep it like that though, so unify them into 'mach/gt64120.h'. Signed-off-by: Denis Orlov

[PATCH 12/21] MIPS: pbl: make sure to disable interrupts/watchpoints on entry

The first thing that we should do on entry is to disable interrupts and watchpoints, as who knows in what state we got there. The former was not being done consistently on every board, while the latter was only being done in the barebox proper for some reason. Add a macro that combines both of

[PATCH 06/21] MIPS: cpuinfo: use appropriate format specifiers in printf

Signed-off-by: Denis Orlov --- arch/mips/lib/cpuinfo.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/lib/cpuinfo.c b/arch/mips/lib/cpuinfo.c index fd27920f9b..41ec7b8d53 100644 --- a/arch/mips/lib/cpuinfo.c +++ b/arch/mips/lib/cpuinfo.c @@ -25,12 +25,12 @@

[PATCH 00/21] MIPS: semi-random code improvements

Denis Orlov (21): MIPS: addrspace: rectify ksseg segment naming MIPS: addrspace: simplify the header MIPS: main_entry-pbl: remove unused variable MIPS: barebox.lds: remove extra whitespace MIPS: reloc: mark relocate_code() as noreturn MIPS: cpuinfo: use appropriate format specifiers in

[PATCH 07/21] MIPS: print BadVAddr CP0 register on exception

This register contains the failing address on Address Error and some TLB-related exceptions, and is useful for debugging purposes. Signed-off-by: Denis Orlov --- arch/mips/include/asm/stackframe.h | 4 arch/mips/lib/traps.c | 3 ++- 2 files changed, 6 insertions(+), 1

[PATCH 02/21] MIPS: addrspace: simplify the header

Deduplicate some of the definitions for 32/64-bit targets and make KSEG* 32-bit defines available for 64-bit builds, as those might still be useful in certain cases. Signed-off-by: Denis Orlov --- arch/mips/include/asm/addrspace.h | 45 ++- 1 file changed, 20

[PATCH 05/21] MIPS: reloc: mark relocate_code() as noreturn

After relocating the code we jump straight to it, with the function having an 'unreachable()' call at the end. So add an appropriate attribute. Signed-off-by: Denis Orlov --- arch/mips/lib/reloc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/lib/reloc.c

[PATCH] bootchooser: honour reset source

With some systems it is possible to determine the source that triggered the most recent reset (see $global.system.reset). This information can be used at the subsequent boot to evaluate whether the respective target works as intended by defining reset reasons that are to be used exclusively. Any

[PATCH] mfd: regulator: initial support for pca9450

The PCA9450 PMIC by NXP can be communicated with via I2C; this driver uses that do determine the reset source that caused the PMIC to perform its latest power cycle. Signed-off-by: Holger Assmann --- drivers/mfd/Kconfig | 7 +++ drivers/mfd/Makefile | 1 + drivers/mfd/pca9450.c | 106