On 05.09.23 16:26, Ahmad Fatoum wrote:
> We have 32K of RAM at the end of the initial memory, where a
> prebootloader can place data for future use. i.MX8M is currently the
> only user and currently uses it to save the ROM API log, which is
> located in SRAM and is inaccessible by the time barebox
We have 32K of RAM at the end of the initial memory, where a
prebootloader can place data for future use. i.MX8M is currently the
only user and currently uses it to save the ROM API log, which is
located in SRAM and is inaccessible by the time barebox proper runs
in EL2. This area was so far not
$(wildcard $(fwdir)/%) was added to allow for optional firmware, but in
return it broke dependency tracking, because it was evaluated before the
static pattern rule it's a part of.
Fix the dependency tracking by only evaluating it in a secondary
expansion. That this works as expected can be
On 9/5/23 14:26, Sascha Hauer wrote:
On Tue, Sep 05, 2023 at 09:57:21AM +0200, Johannes Zink wrote:
Hi Sascha,
On 9/4/23 10:19, Sascha Hauer wrote:
On Tue, Aug 29, 2023 at 04:38:32PM +0200, Johannes Zink wrote:
crc32 may be required in PBL for checking data integrity. Add it to PBL
when
On Tue, Sep 05, 2023 at 09:57:21AM +0200, Johannes Zink wrote:
> Hi Sascha,
>
> On 9/4/23 10:19, Sascha Hauer wrote:
> > On Tue, Aug 29, 2023 at 04:38:32PM +0200, Johannes Zink wrote:
> > > crc32 may be required in PBL for checking data integrity. Add it to PBL
> > > when CONFIG_CRC32 is enabled.
On Tue, Aug 29, 2023 at 02:43:53PM +0200, Marco Felsch wrote:
> On the Debix SBC the EQOS interface is used as primary interface, the
> FEC pins are routed to the extension header. On the other hand the Debix
> SoM/Baseboard combination both interfaces are used. So fix the RGMII pin
> setup by
On 23-09-04, Ahmad Fatoum wrote:
> Lack of clock can be ok at times and thus the clk API accepts NULL
> arguments and treats them as no-op.
>
> Linux provides a clk_get_optional function to simplify code with such
> optional code, so let's provide an equivalent for barebox.
>
> Signed-off-by:
On 23-09-04, Ahmad Fatoum wrote:
> This is a port of Linux commit 9f4c8f9607c3147d291b70c13dd01c738ed41faf:
>
> | Author: Anson Huang
> | AuthorDate: Wed Dec 19 05:24:58 2018 +
> | Commit: Thierry Reding
> | CommitDate: Mon Dec 24 12:06:56 2018 +0100
> |
> | pwm: imx: Add ipg
At the moment the whole available memory is added to one single memory
bank "ram0". This can cause barebox chainload issues on devices with a
huge amount of memory like the i.MX8MP-EVK which has 6G of RAM if the
barebox pbl binary is to large.
The reason for this issues is that
On 31.08.23 11:41, Alexander Shiyan wrote:
>>> +struct id_eeprom {
>>> + u8 hrcw_primary[0x10];
>>> + u8 pn[64];
>>> + u8 sn[64];
>>> + u8 mac0[6];
>>> + u8 mac1[6];
>>> +} __packed;
>>
>> You could describe this as nvmem-cells in the DT and you'd automatically
>> get the MAC
On 23-09-04, Sascha Hauer wrote:
> Hi Marco,
>
> On Thu, Aug 31, 2023 at 04:47:24PM +0200, Marco Felsch wrote:
> > At the moment the whole available memory is added to one single memory
> > bank "ram0". This can cause barebox chainload issues on devices with a
> > huge amount of memory like the
On 23-09-04, Ahmad Fatoum wrote:
> On 31.08.23 16:47, Marco Felsch wrote:
> > At the moment the whole available memory is added to one single memory
> > bank "ram0". This can cause barebox chainload issues on devices with a
> > huge amount of memory like the i.MX8MP-EVK which has 6G of RAM if the
Hi Sascha,
On 9/4/23 10:19, Sascha Hauer wrote:
On Tue, Aug 29, 2023 at 04:38:32PM +0200, Johannes Zink wrote:
crc32 may be required in PBL for checking data integrity. Add it to PBL
when CONFIG_CRC32 is enabled.
To save some memory use a slower-but-smaller variant of the crc32 algorithm
in
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