After applying this patch the last register is writable, but still not
readable.
The size is now correct:
barebox:/ ls -l /dev/stm32-bsec
crw---384 /dev/stm32-bsec
This now works:
mw -l -d /dev/stm32-bsec 0x017c+4 0x12345678
This still doesn't:
barebox:/ md -l -s
Hello Bastian,
On 19.12.23 18:00, Bastian Krause wrote:
> This allows lowlevel board code to use these symbols to perform power
> sequencing with the PBL PMIC helper functions.
>
> Signed-off-by: Bastian Krause
> ---
> drivers/mfd/rn5t568.c | 24 +---
> include/mfd/rn5t568.h | 132
This allows lowlevel board code to use these symbols to perform power
sequencing with the PBL PMIC helper functions.
Signed-off-by: Bastian Krause
---
drivers/mfd/rn5t568.c | 24 +---
include/mfd/rn5t568.h | 132 ++
2 files changed, 133
Hello Bastian,
On 19.12.23 17:11, Bastian Krause wrote:
> Add a common PMIC read function to PBL which allows easy porting of
> U-Boot's pmic_reg_read() in lowlevel board code.
>
> Signed-off-by: Bastian Krause
> ---
> include/pbl/pmic.h | 21 +
> 1 file changed, 21
Add a common PMIC read function to PBL which allows easy porting of
U-Boot's pmic_reg_read() in lowlevel board code.
Signed-off-by: Bastian Krause
---
include/pbl/pmic.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/include/pbl/pmic.h b/include/pbl/pmic.h
index
We should add 1 to the max_register index since counting is zero based.
i.e. the stm32mp151 bsec has registers 0 - 95 with reg_stride 4.
Size should be (95 + 1) * 4 = 384 bytes otherwise we can't access bsec
register 95 (last one).
Signed-off-by: Robin van der Gracht
---
drivers/nvmem/regmap.c
Signed-off-by: Sascha Hauer
---
include/net.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/net.h b/include/net.h
index 83fb4def5d..40287a3503 100644
--- a/include/net.h
+++ b/include/net.h
@@ -49,7 +49,6 @@ struct eth_device {
/* Set promiscuous mode */
int
Signed-off-by: Sascha Hauer
---
drivers/mci/imx-esdhc.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index d2a590a967..fb52c7b893 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -408,11
Signed-off-by: Sascha Hauer
---
drivers/clk/clk-qoric.c | 69 +
1 file changed, 69 insertions(+)
diff --git a/drivers/clk/clk-qoric.c b/drivers/clk/clk-qoric.c
index 49859077f6..6c69b5b3f3 100644
--- a/drivers/clk/clk-qoric.c
+++ b/drivers/clk/clk-qoric.c
Cosmetic change to keep the chipinfo entries ordered.
Signed-off-by: Sascha Hauer
---
drivers/clk/clk-qoric.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/clk-qoric.c b/drivers/clk/clk-qoric.c
index 895810ccd1..49859077f6 100644
---
Adding clk support for LS1028a is straight forward. The changes are
directly imported from Linux.
Sascha Hauer (2):
clk: layerscape: move chipinfo_ls1012a further up
clk: layerscape: add support for ls1028a
drivers/clk/clk-qoric.c | 83 +
1 file
The existing DDR driver can be re-used for LS1028a. We just have to swap
the endianess of the register accesses.
Sascha Hauer (2):
fsl-ddr: remove duplicate prototype
fsl-ddr: make endianess runtime decision
arch/arm/boards/ls1021aiot/lowlevel.c | 2 +-
Signed-off-by: Sascha Hauer
---
arch/arm/boards/ls1021aiot/lowlevel.c | 2 +-
arch/arm/boards/ls1046ardb/lowlevel.c | 2 +-
arch/arm/boards/tqmls1046a/lowlevel.c | 2 +-
drivers/ddr/fsl/arm_ddr_gen3.c| 7 ++-
drivers/ddr/fsl/fsl_ddr_gen4.c| 7 ++-
drivers/ddr/fsl/main.c
Signed-off-by: Sascha Hauer
---
drivers/ddr/fsl/fsl_ddr.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/ddr/fsl/fsl_ddr.h b/drivers/ddr/fsl/fsl_ddr.h
index e95cea1657..0c1a30a236 100644
--- a/drivers/ddr/fsl/fsl_ddr.h
+++ b/drivers/ddr/fsl/fsl_ddr.h
@@ -189,7 +189,6 @@ static inline
The fman OF fixup is registered independent of the actual devices, so
do not assume there are any "fsl,fman" compatible nodes in the current
device tree.
Signed-off-by: Sascha Hauer
---
drivers/net/fsl-fman.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/net/fsl-fman.c
Add "sy" argument to the dmb instruction. This is optional for ARMv7,
but mandatory for ARMv8. On ARMv7 "dsb" and "dsb sy" are equivalent,
so use "dsb sy" on both ARMv7 and ARMv8 and drop the unnecessary #ifdef
Signed-off-by: Sascha Hauer
---
arch/arm/include/asm/system.h | 6 +-
1 file
PowerPC support has never been tested in the pblimage tool and will
hopefully be never needed. Drop its support from pblimage
Signed-off-by: Sascha Hauer
---
scripts/pblimage.c | 22 +-
1 file changed, 5 insertions(+), 17 deletions(-)
diff --git a/scripts/pblimage.c
The PBL images for the LS1028a are a bit different from the ones for the
LS1046a, but can be supported in the same pblimage tool. This adds
support for the LS1028a. To accomplish this the SoC type has to be
passed on the command line, so adjust the Makefiles calling pblimage
accordingly.
next_pbl_cmd is a global static variable that is initialized multiple
times, but used in a single function only. Instead of obfuscating its
usage, just pass its value as a parameter to generate_pbl_cmd().
Signed-off-by: Sascha Hauer
---
scripts/pblimage.c | 23 ---
1 file
We already have roundup() defined in linux/kernel.h, so use it instead
of adding a local definition.
Signed-off-by: Sascha Hauer
---
scripts/pblimage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/pblimage.c b/scripts/pblimage.c
index d0a589f2fe..e8108bbb17 100644
The pblimage tool can be re-used for upcoming LS1028a support. This
series contains the necessary changes for the tool.
Sascha Hauer (4):
pblimage: drop PowerPC support
pblimage: simplify a bit
pblimage: use roundup() from kernel.h
pblimage: Add LS1028a support
These patches will be needed for upcoming Layerscape LS1028a support.
This SoC has the Ethernet Complex in an Integrated Endpoint Root
Complex.
Sascha Hauer (6):
pci: remove duplicate definition of pci_resource_start
pci: Do not register device tree disabled devices
pci: layerscape: limit
BIT(7) of dev->hdr_type has unrelated information. Mask out the upper
bit so that the capabilities can properly be found.
Signed-off-by: Sascha Hauer
---
drivers/pci/pci.c| 4 ++--
include/linux/pci_regs.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git
This will be needed for upcoming LS1028a support. The code is taken from
U-Boot which suffices for our usecase. The kernel code is much more
elaborated here.
Signed-off-by: Sascha Hauer
---
drivers/pci/pci.c | 32
include/linux/pci.h | 2 ++
2 files changed,
ls_pcie_fixup() assumes the fixed up device is attached to the layerscape
PCI controller. This may not be true when there's another controller
active in the system, so limit the execution of the fixup to the right
controller only.
Signed-off-by: Sascha Hauer
---
drivers/pci/pci-layerscape.c | 3
Some PCI devices have device nodes associated with them. Do not register
these devices when they are disabled in the device tree.
Signed-off-by: Sascha Hauer
---
drivers/pci/bus.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index
Some PCI devices have their base addresses not defined in the BARs,
but instead have them defined in Enhanced Allocation structures.
Add support for these Enhanced Allocation structures, taken directly
from the Linux Kernel.
Motivation for adding this is the LS1028a SoC which uses Enhanced
pci_resource_start is defined twice. Remove the duplicate.
Signed-off-by: Sascha Hauer
---
include/linux/pci.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 98d056624f..0e907209a7 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
28 matches
Mail list logo
