Re: 'of_compatible' and 'model' imd records are unusable

On Fri, 1 Oct 2021 14:46:19 +0300 Antony Pavlov wrote: Hi all! > I have cloned barebox c67ada0024da (v2021.08.0) and found that > 'of_compatible' and 'model' imd records are unusable. I have found a quick-and-dirty solution for the problem. of_compatible and model imd types were intr

'of_compatible' and 'model' imd records are unusable

duser@ae676260680c:~/barebox$ -- Best regards,   Antony Pavlov ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox

Re: Fwd: [PATCH] serial: implement riscv SBI console support

*priv; > + > + priv = dev->priv = xzalloc(sizeof(*priv)); > + priv->cdev.dev= dev; > + priv->cdev.putc = sbi_serial_putc; > + priv->cdev.getc = sbi_serial_getc; > + priv->cdev.tstc = sbi_serial_tstc; > + pri

Re: [PATCH RESEND v4 7/8] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support

On Mon, 23 Aug 2021 14:06:09 +0200 Ahmad Fatoum wrote: Hi Ahmad! > On 17.08.21 12:11, Antony Pavlov wrote: > > LiteX is a Migen-based System on Chip, supporting softcore > > VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. > > > > See https://github.com/enjoy-

Re: [PATCH RESEND v4 1/8] clocksource: timer-riscv: select CSR from device tree

On Mon, 23 Aug 2021 14:08:52 +0200 Ahmad Fatoum wrote: Hi Ahmad! > On 17.08.21 12:10, Antony Pavlov wrote: > > barebox timer-riscv driver supports one of user counters: > > > > * 'cycle', counter for RDCYCLE instruction (CSR 0xc00); > > * 'time', timer for RD

Re: [PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon

On Wed, 11 Aug 2021 10:52:53 +0200 Ahmad Fatoum wrote: Hi Ahmad! > Hello Antony, > > On 25.05.21 09:19, Antony Pavlov wrote: > > Changes since v2: > > > > * rebase on top of master branch (f873c7ff2497) + > > "RISC-V: extend multi-image to sup

[PATCH RESEND v4 7/8] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support

LiteX is a Migen-based System on Chip, supporting softcore VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. See https://github.com/enjoy-digital/litex and https://github.com/litex-hub/linux-on-litex-vexriscv for details. Signed-off-by: Antony Pavlov --- arch/riscv/Kconfig.socs

[PATCH RESEND v4 5/8] spi: add litex spiflash driver

Signed-off-by: Antony Pavlov --- drivers/spi/Kconfig | 3 + drivers/spi/Makefile | 1 + drivers/spi/litex_spiflash.c | 241 +++ 3 files changed, 245 insertions(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 91083ee709

[PATCH RESEND v4 8/8] RISC-V: add litex_linux_defconfig

Signed-off-by: Antony Pavlov --- arch/riscv/configs/litex_linux_defconfig | 75 1 file changed, 75 insertions(+) diff --git a/arch/riscv/configs/litex_linux_defconfig b/arch/riscv/configs/litex_linux_defconfig new file mode 100644 index 00..8e19964890 --- /dev

[PATCH RESEND v4 3/8] console: support set baudrate for fixed baudrate drivers

discussion here: http://lists.infradead.org/pipermail/barebox/2021-May/036237.html Signed-off-by: Antony Pavlov --- common/console.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/common/console.c b/common/console.c index ad1a6aaab2..c902239e31 100644 --- a/common

[PATCH RESEND v4 4/8] gpio: add driver for 74xx-ICs with MMIO access

(Output) 8 bits: 74244 (Input), 74273 (Output) 16 bits: 741624 (Input), 7416374 (Output) Signed-off-by: Antony Pavlov Cc: Alexander Shiyan --- drivers/gpio/Kconfig | 14 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-74xx-mmio.c | 165

[PATCH RESEND v4 6/8] net: add LiteEth driver

for details. Signed-off-by: Antony Pavlov Signed-off-by: Marek Czerski --- drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/liteeth.c | 376 ++ 3 files changed, 385 insertions(+) diff --git a/drivers/net/Kconfig b/drivers/net

[PATCH RESEND v4 2/8] serial: add litex UART driver

Signed-off-by: Antony Pavlov --- drivers/serial/Makefile | 1 + drivers/serial/serial_litex.c | 96 +++ 2 files changed, 97 insertions(+) diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 5120b17376..45055371ea 100644 --- a/drivers

[PATCH RESEND v4 1/8] clocksource: timer-riscv: select CSR from device tree

CPU core supports only the 'cycle' counter. VexRiscV CPU core in M-mode supports only the 'time' timer. This patch makes it possible to use the 'time' timer for VexRiscV CPU in M-mode. See also http://lists.infradead.org/pipermail/barebox/2021-May/036067.html Signed-off-by: Antony Pavlov

[PATCH RESEND v4 0/8] RISC-V: add LiteX SoC support

sions are dropped); * NOT FIXED: gpio-74xx-mmio still uses dev_get_drvdata(), not device_get_match_data() Antony Pavlov (8): clocksource: timer-riscv: select CSR from device tree serial: add litex UART driver console: support set baudrate for fixed baudrate drivers gpio: add driver for 7

Re: [PATCH 0/8 v4] RISC-V: add LiteX SoC support

On Tue, 17 Aug 2021 13:04:27 +0300 Antony Pavlov wrote: I have used git format-patch in a inproper way. Sorry! I'll resend the patchseries. > Changes since v3: > > * rebased on top of next branch; > * the "console: support set baudrate for fixed baudra

[PATCH 5/8] spi: add litex spiflash driver

Signed-off-by: Antony Pavlov --- drivers/spi/Kconfig | 3 + drivers/spi/Makefile | 1 + drivers/spi/litex_spiflash.c | 241 +++ 3 files changed, 245 insertions(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 91083ee709

[PATCH 8/8] RISC-V: add litex_linux_defconfig

Signed-off-by: Antony Pavlov --- arch/riscv/configs/litex_linux_defconfig | 75 1 file changed, 75 insertions(+) diff --git a/arch/riscv/configs/litex_linux_defconfig b/arch/riscv/configs/litex_linux_defconfig new file mode 100644 index 00..8e19964890 --- /dev

[PATCH 7/8] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support

LiteX is a Migen-based System on Chip, supporting softcore VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. See https://github.com/enjoy-digital/litex and https://github.com/litex-hub/linux-on-litex-vexriscv for details. Signed-off-by: Antony Pavlov --- arch/riscv/Kconfig.socs

[PATCH 3/8] console: support set baudrate for fixed baudrate drivers

discussion here: http://lists.infradead.org/pipermail/barebox/2021-May/036237.html Signed-off-by: Antony Pavlov --- common/console.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/common/console.c b/common/console.c index ad1a6aaab2..c902239e31 100644 --- a/common

[PATCH 4/8] gpio: add driver for 74xx-ICs with MMIO access

(Output) 8 bits: 74244 (Input), 74273 (Output) 16 bits: 741624 (Input), 7416374 (Output) Signed-off-by: Antony Pavlov Cc: Alexander Shiyan --- drivers/gpio/Kconfig | 14 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-74xx-mmio.c | 165

[PATCH 6/8] net: add LiteEth driver

for details. Signed-off-by: Antony Pavlov Signed-off-by: Marek Czerski --- drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/liteeth.c | 376 ++ 3 files changed, 385 insertions(+) diff --git a/drivers/net/Kconfig b/drivers/net

[PATCH 1/8] clocksource: timer-riscv: select CSR from device tree

CPU core supports only the 'cycle' counter. VexRiscV CPU core in M-mode supports only the 'time' timer. This patch makes it possible to use the 'time' timer for VexRiscV CPU in M-mode. See also http://lists.infradead.org/pipermail/barebox/2021-May/036067.html Signed-off-by: Antony Pavlov

[PATCH 0/8 v4] RISC-V: add LiteX SoC support

sions are dropped); * NOT FIXED: gpio-74xx-mmio still uses dev_get_drvdata(), not device_get_match_data() Antony Pavlov (8): clocksource: timer-riscv: select CSR from device tree serial: add litex UART driver console: support set baudrate for fixed baudrate drivers gpio: add driver for 7

[PATCH 2/8] serial: add litex UART driver

Signed-off-by: Antony Pavlov --- drivers/serial/Makefile | 1 + drivers/serial/serial_litex.c | 96 +++ 2 files changed, 97 insertions(+) diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 5120b17376..45055371ea 100644 --- a/drivers

[PATCH next 3/3] RISC-V: boards: beaglev: make it possible to use nmon

Signed-off-by: Antony Pavlov --- arch/riscv/Kconfig.socs | 1 + arch/riscv/boards/beaglev/lowlevel.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index de74f216a2..221ea133d4 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch

[PATCH next 1/3] RISC-V: make it possible to run nmon from PBL C code

After migrating to PBL we can't use nmon assembler macro in C code anymore. Some changes are introduced to invoke nmon from PBL C code: * use 'lla' macro instruction instead of 'la'; * don't touch the 'ra' register, use 'a2' instead; * add wrapper C function for nmon. Signed-off-by: Antony

[PATCH next 2/3] RISC-V: boards: erizo: make it possible to use nmon

Signed-off-by: Antony Pavlov Reviewed-by: Ahmad Fatoum --- arch/riscv/boards/erizo/lowlevel.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boards/erizo/lowlevel.c b/arch/riscv/boards/erizo/lowlevel.c index fc262ed61b..ab06634bdb 100644 --- a/arch/riscv/boards/erizo

[PATCH next 0/3] RISC-V: resurrect nmon

After migrating to PBL we can't use nmon assembler macro in C code anymore. This series adds necessary wrapper for invoking nmon from PBL C code. Antony Pavlov (3): RISC-V: make it possible to run nmon from PBL C code RISC-V: boards: erizo: make it possible to use nmon RISC-V: boards

[PATCH] Documentation: RISC-V: erizo: fix header level

The "Running on DE0-Nano FPGA board" is a "Erizo" subsection not independent section. Signed-off-by: Antony Pavlov --- Documentation/boards/riscv.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/boards/riscv.rst b/Documentation/bo

[PATCH] drivers: drop unused usb_gadget_{map,unmap}_request()

There is no code that is dependent on usb_gadget_{map,unmap}_request(). Signed-off-by: Antony Pavlov --- drivers/usb/gadget/udc-core.c | 55 --- include/usb/gadget.h | 10 --- 2 files changed, 65 deletions(-) diff --git a/drivers/usb/gadget/udc

[PATCH 0/2] mtd: core: fix use of uninitialized struct member

Antony Pavlov (2): mtd: core: fix use of uninitialized struct member mtd: core: fix whitespaces drivers/mtd/core.c | 32 +--- 1 file changed, 17 insertions(+), 15 deletions(-) -- 2.32.0.rc0 ___ barebox mailing list

[PATCH 2/2] mtd: core: fix whitespaces

Signed-off-by: Antony Pavlov --- drivers/mtd/core.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/core.c b/drivers/mtd/core.c index 98820dfb4f..2029e06d9e 100644 --- a/drivers/mtd/core.c +++ b/drivers/mtd/core.c @@ -377,7 +377,7 @@ int

[PATCH 1/2] mtd: core: fix use of uninitialized struct member

E.g. mtd_read() calls mtd_read_oob(), mtd_read_oob() can check uninitialized ops->oobbuf. As a result mtd_read_oob() can return -EOPNOTSUPP. Found on a MIPS board during /dev/m25p0 read, e.g. barebox:/ md -s /dev/m25p0 read: error 95 Signed-off-by: Antony Pavlov --- drivers/mtd/cor

Re: [PATCH] ARM: SoCFPGA: add Terasic DE10-Nano board support

icense for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + -- Best regards,   Antony Pavlov ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH v3 09/10] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support

On Tue, 25 May 2021 09:47:05 +0200 Jan Lübbe wrote: > On Tue, 2021-05-25 at 10:19 +0300, Antony Pavlov wrote: > > LiteX is a Migen-based System on Chip, supporting softcore > > VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. > > > > See https://github.com/enjoy-

Re: [PATCH v3 05/10] litex serial: add setbrg callback

On Tue, 25 May 2021 10:19:47 +0300 Antony Pavlov wrote: Hi all! > From: Marek Czerski > > setbrg callback (set baudrate) is needed by the loadx/loady commands. > Because litex serial has fixed baudrate the callback only checks if > the requested baudrate is the same as the

[PATCH v3 09/10] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support

LiteX is a Migen-based System on Chip, supporting softcore VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. See https://github.com/enjoy-digital/litex and https://github.com/litex-hub/linux-on-litex-vexriscv for details. Signed-off-by: Antony Pavlov --- arch/riscv/Kconfig.socs

[PATCH v3 10/10] RISC-V: add litex_linux_defconfig

Signed-off-by: Antony Pavlov --- arch/riscv/configs/litex_linux_defconfig | 76 1 file changed, 76 insertions(+) diff --git a/arch/riscv/configs/litex_linux_defconfig b/arch/riscv/configs/litex_linux_defconfig new file mode 100644 index 00..c93a9cb57c --- /dev

[PATCH v3 08/10] net: add LiteEth driver

for details. Signed-off-by: Antony Pavlov Signed-off-by: Marek Czerski --- drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/liteeth.c | 376 ++ 3 files changed, 385 insertions(+) diff --git a/drivers/net/Kconfig b/drivers/net

[PATCH v3 06/10] gpio: add driver for 74xx-ICs with MMIO access

(Output) 8 bits: 74244 (Input), 74273 (Output) 16 bits: 741624 (Input), 7416374 (Output) Signed-off-by: Antony Pavlov Cc: Alexander Shiyan --- drivers/gpio/Kconfig | 14 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-74xx-mmio.c | 165

[PATCH v3 07/10] spi: add litex spiflash driver

Signed-off-by: Antony Pavlov --- drivers/spi/Kconfig | 3 + drivers/spi/Makefile | 1 + drivers/spi/litex_spiflash.c | 241 +++ 3 files changed, 245 insertions(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 323d93efeb

[PATCH v3 04/10] serial: add litex UART driver

Signed-off-by: Antony Pavlov --- drivers/serial/Makefile | 1 + drivers/serial/serial_litex.c | 96 +++ 2 files changed, 97 insertions(+) diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 5120b17376..45055371ea 100644 --- a/drivers

[PATCH v3 05/10] litex serial: add setbrg callback

From: Marek Czerski setbrg callback (set baudrate) is needed by the loadx/loady commands. Because litex serial has fixed baudrate the callback only checks if the requested baudrate is the same as the CONFIG_BAUDRATE. --- drivers/serial/serial_litex.c | 9 - 1 file changed, 8

[PATCH v3 03/10] RISC-V: boards: erizo: make it possible to use nmon

Signed-off-by: Antony Pavlov Reviewed-by: Ahmad Fatoum --- arch/riscv/boards/erizo/lowlevel.c | 4 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boards/erizo/lowlevel.c b/arch/riscv/boards/erizo/lowlevel.c index fc262ed61b..e75a87466a 100644 --- a/arch/riscv/boards/erizo

[PATCH v3 02/10] RISC-V: make it possible to run nmon from PBL C code

After migrating to PBL we can't use nmon assembler macro in C code anymore. Some changes are introduced to invoke nmon from PBL C code: * use 'lla' macro instruction instead of 'la'; * don't touch the 'ra' register, use 'a2' instead; * add wrapper C function for nmon. Signed-off-by: Antony

[PATCH v3 01/10] clocksource: timer-riscv: select CSR from device tree

CPU core supports only the 'cycle' counter. VexRiscV CPU core in M-mode supports only the 'time' timer. This patch makes it possible to use the 'time' timer for VexRiscV CPU in M-mode. Signed-off-by: Antony Pavlov --- arch/riscv/dts/erizo.dtsi | 2 ++ drivers/clocksource/timer-riscv.c

[PATCH v3 00/10] RISC-V: add LiteX SoC support; resurrect nmon

* NOT FIXED: gpio-74xx-mmio still uses dev_get_drvdata(), not device_get_match_data() Antony Pavlov (9): clocksource: timer-riscv: select CSR from device tree RISC-V: make it possible to run nmon from PBL C code RISC-V: boards: erizo: make it possible to use nmon serial: add litex UART driv

[PATCH v2] net: dns: use correct nameserver var name in error message

The commit d5d342d26368c1 ("net: Make domainname and nameserver globalvars") changes net.nameserver variable name to global.net.nameserver. This commit changes the variable name in the error message too. Signed-off-by: Antony Pavlov --- net/dns.c | 2 +- 1 file changed, 1 inser

[PATCH] net: dns: user corrent nameserver var name in error message

The commit d5d342d26368c1 ("net: Make domainname and nameserver globalvars") changes net.nameserver variable name to global.net.nameserver. This commit change the variable name in the error message too. Signed-off-by: Antony Pavlov --- net/dns.c | 2 +- 1 file changed, 1 inser

Re: [PATCH 2/2] RISC-V: extend multi-image to support both S- and M-Mode

also be adapted to use riscv_mode(). > -- Best regards,   Antony Pavlov ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox

[PATCH v2] startup: introduce global.endianness variable

The global.endianness variable makes it possible to determine current endian mode from command line or from script on bi-endian capable system. Signed-off-by: Antony Pavlov --- common/globalvar.c | 13 + 1 file changed, 13 insertions(+) diff --git a/common/globalvar.c b/common

Re: [PATCH] startup: introduce global.endianness variable

On Mon, 3 May 2021 13:16:43 +0200 Sascha Hauer wrote: Hi Sascha! > On Mon, Apr 26, 2021 at 05:30:25PM +0300, Antony Pavlov wrote: > > The global.endianness variable makes it possible > > to determine current endian mode from command > > line or from script on bi-

Re: [PATCH v2 02/11] RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive

On Fri, 7 May 2021 20:08:48 +0200 Ahmad Fatoum wrote: Hi Ahmad! > On 07.05.21 19:52, Antony Pavlov wrote: > > On Fri, 7 May 2021 16:44:24 +0200 > > Ahmad Fatoum wrote: > > > > Hi Ahmad ! > > > >> Hello Antony, > >> > >> On 07.

Re: [PATCH v2 02/11] RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive

On Fri, 7 May 2021 16:44:24 +0200 Ahmad Fatoum wrote: Hi Ahmad ! > Hello Antony, > > On 07.05.21 16:25, Antony Pavlov wrote: > >> I would really like to have a riscv{32,64}_defconfig that can just build > >> all boards > >> at once. Do you know if

Re: [PATCH v2 01/11] clocksource: timer-riscv: select CSR from device tree

On Fri, 7 May 2021 13:34:30 +0200 Ahmad Fatoum wrote: > Hello Antony, > > On 07.05.21 00:08, Antony Pavlov wrote: > > barebox timer-riscv driver supports one of user counters: > > > > * 'cycle', counter for RDCYCLE instruction (CSR 0xc00); > > * 'time',

Re: [PATCH v2 02/11] RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive

On Fri, 7 May 2021 13:42:00 +0200 Ahmad Fatoum wrote: Hi Ahmad! > Hello, > > On 07.05.21 00:08, Antony Pavlov wrote: > > Signed-off-by: Antony Pavlov > > --- > > arch/riscv/Kconfig | 22 -- > > arch/riscv/Kco

Re: [PATCH v2 05/11] serial: add litex UART driver

On Fri, 7 May 2021 13:45:57 +0200 Ahmad Fatoum wrote: > Hi, > > On 07.05.21 00:08, Antony Pavlov wrote: > > Signed-off-by: Antony Pavlov > > --- > > drivers/serial/Makefile | 1 + > > drivers/serial/serial_litex.c | 96 +++

Re: [PATCH 06/12] RISC-V: erizo: drop mach-erizo directory

On Wed, 5 May 2021 12:21:25 +0200 Ahmad Fatoum wrote: Hi Sascha! > Hello Antony, > > On 05.05.21 12:18, Antony Pavlov wrote: > > On Tue, 27 Apr 2021 22:23:03 +0200 > > Ahmad Fatoum wrote: > > > > Hi Ahmad! > > > > Could you please rebase this

Re: [PATCH v2 00/11] RISC-V: add LiteX SoC support; resurrect nmon

On Fri, 7 May 2021 12:23:47 +0200 Ahmad Fatoum wrote: > On 07.05.21 00:08, Antony Pavlov wrote: > > Changes since v1: > > > > * rebased on top of next branch; > > * new patches are introduced: > > * clocksource: timer-riscv: select CSR from device tree

Re: [PATCH 09/12] gpio: generic: sync with upstream Linux gpio-mmio driver

em_region() (success), but bgpio_map() invokes dev_request_mem_resource_by_name() for the same dev and name again. This time dev_request_mem_resource_by_name() fails. -- Best regards,   Antony Pavlov ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox

[PATCH v2 11/11] RISC-V: make it possible to build RV32I multi-image with DEBUG_LL=n

’: arch/riscv/boards/erizo/lowlevel.c:11:2: error: implicit declaration of function ‘debug_ll_ns16550_init’ [-Werror=implicit-function-declaration] 11 | debug_ll_ns16550_init(); | ^ This patch fixes the problem by using preprocessor's directive. Signed-off-by: Antony

[PATCH v2 09/11] RISC-V: add LiteX SoC and linux-on-litex-vexriscv support

LiteX is a Migen-based System on Chip, supporting softcore VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. See https://github.com/enjoy-digital/litex and https://github.com/litex-hub/linux-on-litex-vexriscv for details. Signed-off-by: Antony Pavlov --- arch/riscv/Kconfig.socs

[PATCH v2 08/11] net: add LiteEth driver

for details. Signed-off-by: Antony Pavlov Signed-off-by: Marek Czerski --- drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/liteeth.c | 376 ++ 3 files changed, 385 insertions(+) diff --git a/drivers/net/Kconfig b/drivers/net

[PATCH v2 07/11] spi: add litex spiflash driver

Signed-off-by: Antony Pavlov --- drivers/spi/Kconfig | 3 + drivers/spi/Makefile | 1 + drivers/spi/litex_spiflash.c | 241 +++ 3 files changed, 245 insertions(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 323d93efeb

[PATCH v2 10/11] RISC-V: add litex_linux_defconfig

Signed-off-by: Antony Pavlov --- arch/riscv/configs/litex_linux_defconfig | 77 1 file changed, 77 insertions(+) diff --git a/arch/riscv/configs/litex_linux_defconfig b/arch/riscv/configs/litex_linux_defconfig new file mode 100644 index 00..211fa4bbce --- /dev

[PATCH v2 04/11] RISC-V: boards: erizo: make it possible to use nmon

Signed-off-by: Antony Pavlov Reviewed-by: Ahmad Fatoum --- arch/riscv/boards/erizo/lowlevel.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boards/erizo/lowlevel.c b/arch/riscv/boards/erizo/lowlevel.c index d9edb530b7..fd899c8679 100644 --- a/arch/riscv/boards/erizo

[PATCH v2 03/11] RISC-V: make it possible to run nmon from PBL C code

After migrating to PBL we can't use nmon assembler macro in C code anymore. Some changes are introduced to invoke nmon from PBL C code: * use 'lla' macro instruction instead of 'la'; * don't touch the 'ra' register, use 'a2' instead; * add wrapper C function for nmon. Signed-off-by: Antony

[PATCH v2 02/11] RISC-V: make RISCV_SBI and RISCV_M_MODE explicitly mutually exclusive

Signed-off-by: Antony Pavlov --- arch/riscv/Kconfig | 22 -- arch/riscv/Kconfig.socs| 4 +++- arch/riscv/configs/erizo_generic_defconfig | 1 + 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/arch/riscv/Kconfig b

[PATCH v2 05/11] serial: add litex UART driver

Signed-off-by: Antony Pavlov --- drivers/serial/Makefile | 1 + drivers/serial/serial_litex.c | 96 +++ 2 files changed, 97 insertions(+) diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 5120b17376..45055371ea 100644 --- a/drivers

[PATCH v2 00/11] RISC-V: add LiteX SoC support; resurrect nmon

* almost all of Ahmad's notes are fixed (e.g. unused header files inclusions are dropped); * NOT FIXED: gpio-74xx-mmio still uses dev_get_drvdata(), not device_get_match_data() Antony Pavlov (11): clocksource: timer-riscv: select CSR from device tree RISC-V: make RISCV_SBI and RISCV_M_MODE

[PATCH v2 01/11] clocksource: timer-riscv: select CSR from device tree

CPU core supports only the 'cycle' counter. VexRiscV CPU core supports only the 'time' timer. This patch makes it possible to use the 'time' timer for VexRiscV CPU in M-mode. Signed-off-by: Antony Pavlov --- arch/riscv/cpu/time.c | 7 +++ arch/riscv/dts/erizo.dtsi | 2

[PATCH v2 06/11] gpio: add driver for 74xx-ICs with MMIO access

(Output) 8 bits: 74244 (Input), 74273 (Output) 16 bits: 741624 (Input), 7416374 (Output) Signed-off-by: Antony Pavlov Cc: Alexander Shiyan --- drivers/gpio/Kconfig | 14 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-74xx-mmio.c | 166

Re: [PATCH 6/9] net: add LiteEth driver

On Thu, 6 May 2021 12:10:38 +0200 Roland Hieber wrote: Hi ! > On Wed, May 05, 2021 at 01:08:57PM +0300, Antony Pavlov wrote: > > LiteEth provides a small footprint and configurable Ethernet core. > > > > LiteEth is part of LiteX libraries whose aims are to lower entry leve

Re: [PATCH 7/9] RISC-V: add initial LiteX SoC support

On Wed, 05 May 2021 12:45:23 +0200 Jan Lübbe wrote: > On Wed, 2021-05-05 at 13:08 +0300, Antony Pavlov wrote: > > LiteX is a Migen-based System on Chip, supporting softcore > > VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. > > > > See https://github.com/enjoy-

Re: [PATCH 5/9] spi: add litex spiflash driver

On Wed, 5 May 2021 12:39:14 +0200 Ahmad Fatoum wrote: Hi Ahmad! > Hello Antony, > > On 05.05.21 12:08, Antony Pavlov wrote: > > Signed-off-by: Antony Pavlov > > --- > > drivers/spi/Kconfig | 3 + > > drivers/spi/Makefile | 1 + > &

Re: [PATCH 8/9] RISC-V: add litex-linux board support

P-block base addresses. So in barebox-litex-linux.img the part "litex-linux" is short name for SoC "linux-on-litex-vexriscv". -- Best regards,   Antony Pavlov ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH 06/12] RISC-V: erizo: drop mach-erizo directory

f --git a/arch/riscv/mach-erizo/include/mach/debug_ll.h > b/arch/riscv/include/asm/debug_ll.h > similarity index 57% > rename from arch/riscv/mach-erizo/include/mach/debug_ll.h > rename to arch/riscv/include/asm/debug_ll.h > index a20acfcdfb79..755ed09786d5 100644 > --- a/arch/riscv/

[PATCH 7/9] RISC-V: add initial LiteX SoC support

LiteX is a Migen-based System on Chip, supporting softcore VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. See https://github.com/enjoy-digital/litex and https://github.com/litex-hub/linux-on-litex-vexriscv for details. Signed-off-by: Antony Pavlov --- arch/riscv/Kconfig

[PATCH 9/9] RISC-V: add litex_linux_defconfig

Signed-off-by: Antony Pavlov --- arch/riscv/configs/litex_linux_defconfig | 76 1 file changed, 76 insertions(+) diff --git a/arch/riscv/configs/litex_linux_defconfig b/arch/riscv/configs/litex_linux_defconfig new file mode 100644 index 00..ab53df1c78 --- /dev

[PATCH 8/9] RISC-V: add litex-linux board support

Tested on Digilent Arty FPGA board. Signed-off-by: Antony Pavlov --- arch/riscv/boards/Makefile | 1 + arch/riscv/boards/litex-linux/Makefile | 3 + arch/riscv/boards/litex-linux/lowlevel.c | 20 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/litex

[PATCH 5/9] spi: add litex spiflash driver

Signed-off-by: Antony Pavlov --- drivers/spi/Kconfig | 3 + drivers/spi/Makefile | 1 + drivers/spi/litex_spiflash.c | 242 +++ 3 files changed, 246 insertions(+) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 323d93efeb

[PATCH 6/9] net: add LiteEth driver

for details. Signed-off-by: Antony Pavlov Signed-off-by: Marek Czerski --- drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/liteeth.c | 376 ++ 3 files changed, 385 insertions(+) Cc: Marek Czerski diff --git a/drivers/net/Kconfig

[PATCH 1/9] RISC-V: make it possible to run nmon from PBL C code

After migrating to PBL we can't use nmon assembler macro in C code anymore. Some changes are introduced to invoke nmon from PBL C code: * use 'lla' macro instruction instead of 'la'; * don't touch the 'ra' register, use 'a2' instead; * add wrapper C function for nmon. Signed-off-by: Antony

[PATCH 4/9] gpio: add driver for 74xx-ICs with MMIO access

(Output) 8 bits: 74244 (Input), 74273 (Output) 16 bits: 741624 (Input), 7416374 (Output) Signed-off-by: Antony Pavlov Cc: Alexander Shiyan --- drivers/gpio/Kconfig | 14 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-74xx-mmio.c | 170

[PATCH 3/9] serial: add litex UART driver

Signed-off-by: Antony Pavlov --- drivers/serial/Makefile | 1 + drivers/serial/serial_litex.c | 96 +++ 2 files changed, 97 insertions(+) diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 7ff41cd5c7..95c3387d3e 100644 --- a/drivers

[PATCH 0/9] RISC-V: add LiteX SoC support; resurrect nmon

Antony Pavlov (9): RISC-V: make it possible to run nmon from PBL C code RISC-V: boards: erizo: make it possible to use nmon serial: add litex UART driver gpio: add driver for 74xx-ICs with MMIO access spi: add litex spiflash driver net: add LiteEth driver RISC-V: add initial LiteX

[PATCH 2/9] RISC-V: boards: erizo: make it possible to use nmon

Signed-off-by: Antony Pavlov --- arch/riscv/boards/erizo/lowlevel.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boards/erizo/lowlevel.c b/arch/riscv/boards/erizo/lowlevel.c index d9edb530b7..185de6ed77 100644 --- a/arch/riscv/boards/erizo/lowlevel.c +++ b/arch/riscv/boards

Re: [PATCH] startup: introduce global.endianness variable

On Mon, 26 Apr 2021 17:30:25 +0300 Antony Pavlov wrote: ping > The global.endianness variable makes it possible > to determine current endian mode from command > line or from script on bi-endian capable system. > > Signed-off-by: Antony Pavlov > --- > common/globalvar.c

Re: [PATCH] scripts/spdxcheck.py: Use Python 3

On Fri, 16 Apr 2021 12:14:04 +0300 Antony Pavlov wrote: ping > Based on this linux kernel commit: > > > commit d0259c42abff51b586496a0594933e394efefbc5 > > Author: Bert Vermeulen > > Date: Thu Jan 21 09:54:12 2021 +0100 > > > >spdxcheck.py: Use Pyt

Re: [PATCH] MIPS: qemu-malta: use generic syscon reset driver

On Sun, 25 Apr 2021 09:35:17 +0300 Antony Pavlov wrote: ping > Signed-off-by: Antony Pavlov > --- > arch/mips/configs/qemu-malta_defconfig | 2 ++ > arch/mips/dts/qemu-malta.dts | 13 +++ > arch/mips/mach-malta/Makefile | 1 - > arch/mips/

[PATCH] startup: introduce global.endianness variable

The global.endianness variable makes it possible to determine current endian mode from command line or from script on bi-endian capable system. Signed-off-by: Antony Pavlov --- common/globalvar.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/common/globalvar.c b/common

[PATCH] MIPS: qemu-malta: use generic syscon reset driver

Signed-off-by: Antony Pavlov --- arch/mips/configs/qemu-malta_defconfig | 2 ++ arch/mips/dts/qemu-malta.dts | 13 +++ arch/mips/mach-malta/Makefile | 1 - arch/mips/mach-malta/reset.c | 31 -- 4 files changed, 15 insertions(+), 32

[PATCH] scripts/spdxcheck.py: Use Python 3

it module for it is hard to come by. Signed-off-by: Antony Pavlov --- scripts/checkpatch.pl | 4 ++-- scripts/spdxcheck.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index b8bd4e1a59..36e3d768f3 100755 --- a/scripts/che

Re: RISC-V: erizo: large gap between bss and stack regions

On Wed, 14 Apr 2021 13:20:44 +0200 Ahmad Fatoum wrote: > On 14.04.21 13:07, Antony Pavlov wrote: > > On Wed, 14 Apr 2021 11:54:27 +0200 > > Sascha Hauer wrote: > > > >> On Wed, Apr 14, 2021 at 08:54:22AM +0300, Antony Pavlov wrote: > >>> Hi Ahmad! &g

Re: RISC-V: erizo: large gap between bss and stack regions

On Wed, 14 Apr 2021 11:54:27 +0200 Sascha Hauer wrote: > On Wed, Apr 14, 2021 at 08:54:22AM +0300, Antony Pavlov wrote: > > Hi Ahmad! > > > > Here is the iomem command output on erizo: > > > > barebox:/ iomem > > 0x - 0x (size 0x00

RISC-V: erizo: large gap between bss and stack regions

ata 0xafffa640 - 0xafffe7ab (size 0x416c) bss -- Best regards,   Antony Pavlov ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox

Re: [PATCH master 1/3] RISC-V: cpu: request stack memory region

On Sat, 3 Apr 2021 09:09:15 +0200 Ahmad Fatoum wrote: > Hello Antony, > > On 02.04.21 10:13, Antony Pavlov wrote: > >> This is strange. Could you print get_runtime_offset() at this location? > >> It should be zero, because relocate_to_current_adr() had previously

Re: [PATCH master] RISC-V: boot: uncompress: determine piggy data bounds before relocation

On Sat, 3 Apr 2021 09:03:32 +0200 Ahmad Fatoum wrote: Hi Ahmad! I have just tested this patch on erizo FPGA. Barebox work fine. -- Best regards, Antony Pavlov > Like on ARM, the PBL common code does not relocate the piggy data and > instead keeps pointers into the old image's lo

Re: [PATCH master 1/3] RISC-V: cpu: request stack memory region

On Fri, 2 Apr 2021 08:34:36 +0200 Ahmad Fatoum wrote: Hi Ahmad! > Hello Antony, > > On 02.04.21 07:56, Antony Pavlov wrote: > > On Wed, 24 Mar 2021 09:23:02 +0100 > > Ahmad Fatoum wrote: > > > > Current RISC-V erizo barebox master succesfully runs on QEMU &g

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