On Wed, Apr 15, 2020 at 08:19:09AM +0200, Michael Tretter wrote:
> Hi Michael,
>
> On Tue, Apr 14, 2020 at 09:23:53PM +0200, Michael Graichen wrote:
> > Am 14.04.20 um 12:53 schrieb Michael Tretter:
> > > On Thu, Apr 09, 2020 at 02:44:00PM +, Michael Graichen wrote:
> > > > This adds support
Hi Michael,
On Tue, Apr 14, 2020 at 09:23:53PM +0200, Michael Graichen wrote:
> Am 14.04.20 um 12:53 schrieb Michael Tretter:
> > On Thu, Apr 09, 2020 at 02:44:00PM +, Michael Graichen wrote:
> > > This adds support to programm the PL part of the Zynq SoC,
> > > but only the non-secure way
Hi Michael,
Am 14.04.20 um 12:53 schrieb Michael Tretter:
Hi Michael,
On Thu, Apr 09, 2020 at 02:44:00PM +, Michael Graichen wrote:
This adds support to programm the PL part of the Zynq SoC,
but only the non-secure way and no partial reconfiguration. It adds the
'zynq_fpga_manager' so we
Hi Michael,
On Thu, Apr 09, 2020 at 02:44:00PM +, Michael Graichen wrote:
> This adds support to programm the PL part of the Zynq SoC,
> but only the non-secure way and no partial reconfiguration. It adds the
> 'zynq_fpga_manager' so we can use
>
> firmwareload -l
> firmwareload -t
This adds support to programm the PL part of the Zynq SoC,
but only the non-secure way and no partial reconfiguration. It adds the
'zynq_fpga_manager' so we can use
firmwareload -l
firmwareload -t zynq-fpga-manager /mnt/mmc0.0/design_1_wrapper.bit
to programm the PL.
Signed-off-by: Michael
