On Tue, Apr 10, 2018 at 04:38:05PM -0700, Andrey Smirnov wrote:
> Signed-off-by: Andrey Smirnov
> ---
> arch/arm/include/asm/barebox-arm.h | 9 +++--
> 1 file changed, 3 insertions(+), 6 deletions(-)
Applied, thanks
Sascha
>
> diff --git
The pblx-y variables for the TX53 have _imx53 twice in their names. With
this the names do not match the names in the FILE_* variables. This
results in the make system removing the pblx files as intermediate
files. Fix the names.
Signed-off-by: Sascha Hauer
---
On Tue, Apr 10, 2018 at 12:53:32PM +0200, Lucas Stach wrote:
> Am Donnerstag, den 05.04.2018, 09:54 +0200 schrieb Sascha Hauer:
> > On Mon, Mar 26, 2018 at 09:20:19PM +0200, Lucas Stach wrote:
> > > This adds routines to add hyp mode vectors and switch back to HYP
> > > mode from SVC. This is
On Mon, Apr 09, 2018 at 06:36:36PM -0700, Andrey Smirnov wrote:
> Latest version of get_runtime_offset() returns positive offset that
> needs to be added to rather than substracted from original pointer.
>
> Cc: Michael Grzeschik
> Signed-off-by: Andrey Smirnov
On Mon, Apr 09, 2018 at 01:53:59PM +0200, Christoph Fritz wrote:
> Add support for Advantech i.MX6 SOM named ROM-7421.
>
> Signed-off-by: Christoph Fritz
> ---
> Changes since v0:
> - distinguish between MMC environment names in pr_notice() board.c
> - rework eMMC
On Tue, Apr 10, 2018 at 04:45:36PM -0700, Andrey Smirnov wrote:
> Avoid calling arm_mem_barebox_image() twice by making barebox_base
> function-wide in scope
>
> Signed-off-by: Andrey Smirnov
> ---
> arch/arm/cpu/start.c | 13 +
> 1 file changed, 5
Based on the corresponding Kernel code:
The gpmi needs 100MHz frequency in the EDO/Sync mode, We can not get the
100MHz from the pll2_pfd0_352m. So choose pll2_pfd2_396m as enfc_sel's
parent.
Signed-off-by: Sascha Hauer
---
drivers/clk/imx/clk-imx6.c | 7 +++
1 file
The i.MX6 phyCORE boards have USBOTG support. Enable it.
Signed-off-by: Sascha Hauer
---
arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
On Mon, Apr 09, 2018 at 09:40:46AM -0700, Andrey Smirnov wrote:
> On Mon, Apr 2, 2018 at 11:54 PM, Sascha Hauer wrote:
> > Hi Andrey,
> >
> > Some comments inside.
> >
> >
> > On Mon, Mar 26, 2018 at 06:09:14AM -0700, Andrey Smirnov wrote:
> >> Port 'serdev' UART-slave
Hi Andrey,
On Mon, Apr 09, 2018 at 09:00:52AM -0700, Andrey Smirnov wrote:
> On Tue, Apr 3, 2018 at 12:04 AM, Sascha Hauer wrote:
> > On Mon, Mar 26, 2018 at 06:09:15AM -0700, Andrey Smirnov wrote:
> >> In order to allow 'serdev' devices to prevent parent console device
>
On Tue, Apr 10, 2018 at 04:40:37PM -0700, Andrey Smirnov wrote:
> Majority of others boards prints '>' as soon as DEBUG_LL related
> configuration is done, so do so for VF610-TWR as well.
>
> Signed-off-by: Andrey Smirnov
> ---
>
On Tue, Apr 10, 2018 at 04:39:43PM -0700, Andrey Smirnov wrote:
> Signed-off-by: Andrey Smirnov
> ---
> drivers/pinctrl/pinctrl-vf610.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Applied, thanks
Sascha
>
> diff --git
On Tue, Apr 10, 2018 at 04:53:13PM -0700, Andrey Smirnov wrote:
> Everyone:
>
> This series is a bit of code I developed to support automatic
> configured DRAM size detection on Vybrid platform as well as some
> small fixes/cleanup I made while looking at esdctl.c.
>
> All feedback is wellcome!
We need to distinguish between the i.MX6d/q and the i.MX6d/q plus SoC
variants. Add a cpu type for them to make that possible in the next
steps.
Signed-off-by: Sascha Hauer
---
arch/arm/boards/phytec-som-imx6/board.c | 2 +-
arch/arm/boards/zii-imx6q-rdu2/lowlevel.c |
The i.MX6sl has another silicon revision register offset than the
other i.MX6 SoCs. Finding the register is done twice. Factor out
a function to get a common place to find the register.
Signed-off-by: Sascha Hauer
---
arch/arm/mach-imx/include/mach/imx6.h | 61
The plus SoC variants have some differences in the clock controller.
For now fix the NAND controller clock. There are more differences
that might be relevant, but for now are left for a future excercise.
Signed-off-by: Sascha Hauer
---
drivers/clk/imx/clk-imx6.c | 19
The i.MX6 plus SoC variants have some changes in the clock controller,
start integrating them beginning with the NAND controller clock.
Before doing so we have to add proper detection code for the i.MX6 plus.
Sascha Hauer (4):
ARM: i.MX6: de-inline i.MX6 type detection
ARM: i.MX6: factor out
Having the i.MX6 type detection completely inline is less then optimal
in terms of binary size. Make the detection functions non-inline. While
at it ask the registers only once and store the result in a variable as
the i.MX6 type is unlikely to change during runtime.
Signed-off-by: Sascha Hauer
Signed-off-by: Antony Pavlov
---
arch/arm/mach-socfpga/include/mach/pll_config.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/pll_config.h
b/arch/arm/mach-socfpga/include/mach/pll_config.h
index 1a7e851eda..d6fb60dd24 100644
Signed-off-by: Antony Pavlov
---
arch/arm/boards/ebv-socrates/pll_config.h | 6 --
arch/arm/boards/terasic-sockit/pll_config.h | 6 --
2 files changed, 12 deletions(-)
diff --git a/arch/arm/boards/ebv-socrates/pll_config.h
Antony Pavlov (4):
net: make SoCFPGA-specific designware driver work again
ARM: socfpga: boards: pll_config.h: remove duplicate macros
ARM: socfpga: mach/pll_config.h: add guard macro
ARM: socfpga_defconfig: enable Altera firmware stuff
arch/arm/boards/ebv-socrates/pll_config.h | 6
Signed-off-by: Antony Pavlov
---
arch/arm/configs/socfpga_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/socfpga_defconfig
b/arch/arm/configs/socfpga_defconfig
index 6883b5f526..3a50bae8f2 100644
--- a/arch/arm/configs/socfpga_defconfig
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