Make more space for long lines which we'll add in the next commit.
Signed-off-by: Roland Hieber
---
Documentation/user/networking.rst | 38 +++
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/Documentation/user/networking.rst
There are use cases where the port and mount path of the NFS root need
to be changed from the default values, e.g. with the userspace NFS
daemon used by 'ptxdist nfsroot', which tells you:
Mount rootfs with nfsroot=/root,v3,tcp,port=13049,mountport=13049
(The port number can vary of course,
On Fri, 2023-02-10 at 17:53 +0100, Ahmad Fatoum wrote:
> FIT public key is usually passed in via board DT. Usual way to use
> barebox with QEMU Virt however is to use DT supplied by Qemu and apply
> overlay to it. mkimage doesn't generate overlay DTB though. To make
> barbebox Qemu Virt behave
Hello Renaud,
On 10.02.23 16:57, Renaud Barbier wrote:
> What about soc/fsl/immap_lsch2.h vs soc/fsl/immap_ls102xa.h.
> Lots of similarities but also a lots of differences (when excluding the
> prefix LSCH2 and LS102XA)
> Can I assume ccsr_scfg can be mapped to each other?
> May be a question to
FIT public key is usually passed in via board DT. Usual way to use
barebox with QEMU Virt however is to use DT supplied by Qemu and apply
overlay to it. mkimage doesn't generate overlay DTB though. To make
barbebox Qemu Virt behave like other boards, let's define a dummy DT
that includes
Qemu board driver fixups should be applied very early to be able to
influence core components, even if they are controlled directly by
initcalls. For this reason, enforce probe of the driver at postcore_initcall
level.
Signed-off-by: Ahmad Fatoum
---
v1 -> v2:
- new patch -- otherwise, probe
Creation of a machine device for the top-level node has special casing
in of_probe(). Export of_platform_device_create_root(), so it's possible
to ensure probe of the machine device. This is required when doing
of_devices_ensure_probed_by_dev_id with the machine compatible.
Signed-off-by: Ahmad
Later commit will need to merge two DTs from the root up. Refactor
that part out of of_copy_node to make it usable on its own.
Signed-off-by: Ahmad Fatoum
---
v1 -> v2:
- no changes
---
drivers/of/base.c | 17 -
include/of.h | 1 +
2 files changed, 13 insertions(+), 5
What about soc/fsl/immap_lsch2.h vs soc/fsl/immap_ls102xa.h.
Lots of similarities but also a lots of differences (when excluding the prefix
LSCH2 and LS102XA)
Can I assume ccsr_scfg can be mapped to each other?
May be a question to NXP.
> -Original Message-
> From: Sascha Hauer
> Sent:
Follow-up commit will need to merge two DTs from the root up. Refactor
that part out of of_copy_node to make it usable on its own.
Signed-off-by: Ahmad Fatoum
---
drivers/of/base.c | 17 -
include/of.h | 1 +
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git
FIT public key is usually passed in via board DT. Usual way to use
barebox with QEMU Virt however is to use DT supplied by Qemu and apply
overlay to it. mkimage doesn't generate overlay DTB though. To make
barbebox Qemu Virt behave like other boards, let's define a dummy DT
that includes
Denis Orlov (4):
MIPS: dma: fix nullptr handling in dma_free_coherent
MIPS: dma: remove unnecessary ifdefs
MIPS: dma: add arch-specific dma_alloc() implementation
MIPS: dma: simplify source structure
arch/mips/include/asm/dma-mapping.h | 40 ---
It is not an error to pass a null pointer to free() and as such it seems
that dma_free_coherent() should be able to handle this situation too.
Currently, if CONFIG_MMU option is enabled, we would convert this null
pointer into a pointer to the beginning of CKSEG0 memory segment before
passing it
There is no reason to keep code from 'dma-mapping.h' in a separate file,
so merge it into 'dma.h'.
Signed-off-by: Denis Orlov
---
arch/mips/include/asm/dma-mapping.h | 40 -
arch/mips/include/asm/dma.h | 31 +-
2 files changed, 30
We do not support any MIPS CPUs that are not MIPS32/MIPS64, so there is
no reason to check for those.
Signed-off-by: Denis Orlov
---
arch/mips/lib/dma-default.c | 8
1 file changed, 8 deletions(-)
diff --git a/arch/mips/lib/dma-default.c b/arch/mips/lib/dma-default.c
index
DMA allocations should be aligned on a cache line size, at least on
cache non-coherent MIPS systems. Instead of using some hardcoded value
for an alignment from a generic implementation (which may be wrong for
us), we can get cache info from 'current_cpu_data' variable, so use it.
Signed-off-by:
The code was assuming that in such cases we can just use cpu addresses
as physical ones. This is incorrect on MIPS, the only platform that has
its own virt_to_phys/phys_to_virt functions defined.
This fixes issues with DMA mappings on MIPS, with e1000 PCI ethernet
card now working on Malta in
With these changes, e1000 driver now works on MIPS Malta in QEMU with
the corresponding network controller attached:
-netdev user,tftp=/tftpboot,id=net0 -device e1000,netdev=net0
Antony Pavlov (1):
net: e1000: properly map dma allocations
Denis Orlov (1):
dma: use virt/phys conversions
From: Antony Pavlov
Signed-off-by: Antony Pavlov
Signed-off-by: Denis Orlov
---
drivers/net/e1000/e1000.h | 2 ++
drivers/net/e1000/main.c | 8
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index
On Fri, Feb 10, 2023 at 11:54:31AM +, Renaud Barbier wrote:
> I have not tried yet. I was not sure if you like to have separate machine
> support as there are some differences in the SOC .
>
> I will merge it and send you a new patch.
I like it better when it's merged, eventhough it's never
On Wed, Feb 08, 2023 at 01:26:30PM +, Renaud Barbier wrote:
> The LS1021A-IOR is a NXP reference board.
> Currently supported:
>
> - DDR3 RAM fixed settings
> - UART
> - SPI boot
> - One SGMII network ports
>
> Signed-off-by: Renaud Barbier
> ---
> arch/arm/boards/Makefile
I have not tried yet. I was not sure if you like to have separate machine
support as there are some differences in the SOC .
I will merge it and send you a new patch.
> -Original Message-
> From: Sascha Hauer
> Sent: 10 February 2023 11:26
> To: Renaud Barbier
> Cc: Barebox List
>
On Wed, Feb 08, 2023 at 01:26:21PM +, Renaud Barbier wrote:
> The LS1021A-IOT is NXP ARMv7 Layerscape evaluation board.
>
> These patches provide a basic board support with:
> - UART
> - boot from SPI
> - One Ethernet port - eth1*
>
> The content of the EEPROM having been
On Thu, Feb 09, 2023 at 05:37:51PM +0300, Denis Orlov wrote:
> Otherwise, we can not access file systems located on partitioned NVME
> drives.
>
> Signed-off-by: Denis Orlov
> ---
> drivers/nvme/host/core.c | 5 +
> 1 file changed, 5 insertions(+)
Applied, thanks
Sascha
>
> diff --git
On Thu, Feb 09, 2023 at 10:56:40AM +0100, Kilian Strasser wrote:
> Function gpioinfo returns wrong gpio values.
> In the file pinctrl.rockchip.c a wrong register offset is used by the
> function rockchip_gpiov2_get_value. Also the bit-mask for this register
> is wrong. Change register offset for
On Wed, Feb 08, 2023 at 02:35:19PM +0100, Lucas Stach wrote:
> From: Ahmad Fatoum
>
> The Polyhex DEBIX Model A is an i.MX8MP based Rpi form factor board.
> This commit imports the v6 of the Linux device tree[1], and the timings
> from the vendor U-Boot[2] and combines it with existing barebox
On Wed, Feb 08, 2023 at 02:35:18PM +0100, Lucas Stach wrote:
> From: Ahmad Fatoum
>
> Signed-off-by: Ahmad Fatoum
> Signed-off-by: Lucas Stach
> ---
> drivers/ddr/imx8m/ddrphy_utils.c | 3 +++
> 1 file changed, 3 insertions(+)
Applied, thanks
Sascha
>
> diff --git
On Wed, Feb 08, 2023 at 02:34:06PM +0100, Lucas Stach wrote:
> All i.MX8M* DDRC nodes are compatible to "fsl,imx8m-ddrc". As the memory
> size detection works the same on most of them, with the only exception
> being the i.MX8MN, which only has a 16bit data bus, there is no need to
> match the
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