Re: [PATCH 1/4] arm: dts: am335x: Add emmc node to phycore-som

[Sascha Hauer]

On Tue, Aug 22, 2017 at 08:44:04AM +0200, Daniel Schultz wrote:
> Add the EMMC node to the phycore-som device tree. It's by default
> disabled, because NAND is the primary boot device.
> 
> Signed-off-by: Daniel Schultz 
> ---
>  arch/arm/dts/am335x-phytec-phycore-som.dtsi | 24 
>  1 file changed, 24 insertions(+)

Applied, thanks

Sascha

> 
> diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi 
> b/arch/arm/dts/am335x-phytec-phycore-som.dtsi
> index 0b8c454..0025bc7 100644
> --- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi
> +++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi
> @@ -58,6 +58,21 @@
>   >;
>   };
>  
> + emmc_pins: pinmux_emmc_pins {
> + pinctrl-single,pins = <
> + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* 
> gpmc_csn1.mmc1_clk */
> + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* 
> gpmc_csn2.mmc1_cmd */
> + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* 
> gpmc_ad0.mmc1_dat0 */
> + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* 
> gpmc_ad1.mmc1_dat1 */
> + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* 
> gpmc_ad2.mmc1_dat2 */
> + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* 
> gpmc_ad3.mmc1_dat3 */
> + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* 
> gpmc_ad4.mmc1_dat4 */
> + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* 
> gpmc_ad5.mmc1_dat5 */
> + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* 
> gpmc_ad6.mmc1_dat6 */
> + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* 
> gpmc_ad7.mmc1_dat7 */
> + >;
> + };
> +
>   emac_rmii1_pins: pinmux_emac_rmii1_pins {
>   pinctrl-single,pins = <
>   0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* 
> mii1_crs.rmii1_crs_dv */
> @@ -157,6 +172,15 @@
>   status = "okay";
>  };
>  
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> + bus-width = <8>;
> + status = "disabled";
> + ti,vcc-aux-disable-is-sleep;
> + non-removable;
> +};
> +
>   {
>   pinctrl-names = "default";
>   pinctrl-0 = <_pins>;
> -- 
> 2.7.4
> 
> 
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[PATCH 1/4] arm: dts: am335x: Add emmc node to phycore-som

[Daniel Schultz]

Add the EMMC node to the phycore-som device tree. It's by default
disabled, because NAND is the primary boot device.

Signed-off-by: Daniel Schultz 
---
 arch/arm/dts/am335x-phytec-phycore-som.dtsi | 24 
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi 
b/arch/arm/dts/am335x-phytec-phycore-som.dtsi
index 0b8c454..0025bc7 100644
--- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi
@@ -58,6 +58,21 @@
>;
};
 
+   emmc_pins: pinmux_emmc_pins {
+   pinctrl-single,pins = <
+   0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* 
gpmc_csn1.mmc1_clk */
+   0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* 
gpmc_csn2.mmc1_cmd */
+   0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* 
gpmc_ad0.mmc1_dat0 */
+   0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* 
gpmc_ad1.mmc1_dat1 */
+   0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* 
gpmc_ad2.mmc1_dat2 */
+   0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* 
gpmc_ad3.mmc1_dat3 */
+   0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* 
gpmc_ad4.mmc1_dat4 */
+   0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* 
gpmc_ad5.mmc1_dat5 */
+   0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* 
gpmc_ad6.mmc1_dat6 */
+   0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* 
gpmc_ad7.mmc1_dat7 */
+   >;
+   };
+
emac_rmii1_pins: pinmux_emac_rmii1_pins {
pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* 
mii1_crs.rmii1_crs_dv */
@@ -157,6 +172,15 @@
status = "okay";
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   bus-width = <8>;
+   status = "disabled";
+   ti,vcc-aux-disable-is-sleep;
+   non-removable;
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
-- 
2.7.4


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