Re: [PATCH 02/10] ARM: i.MX: Add infrastructure to record SoC reset reason

[Andrey Smirnov]

On Wed, Apr 18, 2018 at 8:23 AM, Philipp Zabel  wrote:
> On Sat, 2018-04-14 at 10:50 -0700, Andrey Smirnov wrote:
>> Signed-off-by: Andrey Smirnov 
>> ---
>>  arch/arm/mach-imx/imx.c   | 49 
>> +++
>>  arch/arm/mach-imx/include/mach/reset-reason.h | 17 ++
>>  2 files changed, 66 insertions(+)
>>  create mode 100644 arch/arm/mach-imx/include/mach/reset-reason.h
>>
>> diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
>> index 9400105c6..e860e298a 100644
>> --- a/arch/arm/mach-imx/imx.c
>> +++ b/arch/arm/mach-imx/imx.c
>> @@ -14,8 +14,11 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>> +#include 
>>  #include 
>> +#include 
>>
>>  static int __imx_silicon_revision = IMX_CHIP_REV_UNKNOWN;
>>
>> @@ -147,3 +150,49 @@ static int imx_init(void)
>>   return ret;
>>  }
>>  postcore_initcall(imx_init);
>> +
>> +void imx_set_reset_reason(void __iomem *srsr)
>> +{
>> + enum reset_src_type type = RESET_UKWN;
>> + const u32 reg = readl(srsr);
>> +
>> + /*
>> +  * SRSR register captures ALL reset event that occured since
>> +  * POR, so we need to clear it to make sure we only caputre
>> +  * the latest one.
>> +  */
>> + writel(reg, srsr);
>
> What if, say, both a watchdog and the tempsense reset have triggered
> since last POR (or since last clearing of SRSR)?
> In that case we'll report RESET_UKWN *and* throw away the SRSR
> information here.
>

I am assuming we are talking about the fact that "reg" is decoded
using switch statement, as opposed to doing bitmaksing (like VFxxx
code does). I got the code form U-Boot and that is how it's doing the
decoding, but you are right it is going to be problematic for use-case
you describe.

I'll switch the code to do bitmaksing instead.

Thanks,
Andrey Smrinov

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Re: [PATCH 02/10] ARM: i.MX: Add infrastructure to record SoC reset reason

[Philipp Zabel]

On Sat, 2018-04-14 at 10:50 -0700, Andrey Smirnov wrote:
> Signed-off-by: Andrey Smirnov 
> ---
>  arch/arm/mach-imx/imx.c   | 49 
> +++
>  arch/arm/mach-imx/include/mach/reset-reason.h | 17 ++
>  2 files changed, 66 insertions(+)
>  create mode 100644 arch/arm/mach-imx/include/mach/reset-reason.h
> 
> diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
> index 9400105c6..e860e298a 100644
> --- a/arch/arm/mach-imx/imx.c
> +++ b/arch/arm/mach-imx/imx.c
> @@ -14,8 +14,11 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
> +#include 
>  #include 
> +#include 
>  
>  static int __imx_silicon_revision = IMX_CHIP_REV_UNKNOWN;
>  
> @@ -147,3 +150,49 @@ static int imx_init(void)
>   return ret;
>  }
>  postcore_initcall(imx_init);
> +
> +void imx_set_reset_reason(void __iomem *srsr)
> +{
> + enum reset_src_type type = RESET_UKWN;
> + const u32 reg = readl(srsr);
> +
> + /*
> +  * SRSR register captures ALL reset event that occured since
> +  * POR, so we need to clear it to make sure we only caputre
> +  * the latest one.
> +  */
> + writel(reg, srsr);

What if, say, both a watchdog and the tempsense reset have triggered
since last POR (or since last clearing of SRSR)?
In that case we'll report RESET_UKWN *and* throw away the SRSR
information here.

regards
Philipp

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[PATCH 02/10] ARM: i.MX: Add infrastructure to record SoC reset reason

[Andrey Smirnov]

Signed-off-by: Andrey Smirnov 
---
 arch/arm/mach-imx/imx.c   | 49 +++
 arch/arm/mach-imx/include/mach/reset-reason.h | 17 ++
 2 files changed, 66 insertions(+)
 create mode 100644 arch/arm/mach-imx/include/mach/reset-reason.h

diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
index 9400105c6..e860e298a 100644
--- a/arch/arm/mach-imx/imx.c
+++ b/arch/arm/mach-imx/imx.c
@@ -14,8 +14,11 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
+#include 
 
 static int __imx_silicon_revision = IMX_CHIP_REV_UNKNOWN;
 
@@ -147,3 +150,49 @@ static int imx_init(void)
return ret;
 }
 postcore_initcall(imx_init);
+
+void imx_set_reset_reason(void __iomem *srsr)
+{
+   enum reset_src_type type = RESET_UKWN;
+   const u32 reg = readl(srsr);
+
+   /*
+* SRSR register captures ALL reset event that occured since
+* POR, so we need to clear it to make sure we only caputre
+* the latest one.
+*/
+   writel(reg, srsr);
+
+   switch (reg) {
+   case IMX_SRC_SRSR_IPP_RESET: /* FALLTHROUGH */
+   case IMX_SRC_SRSR_IPP_RESET | IMX_SRC_SRSR_WDOG1_RESET:
+   type = RESET_POR;
+   break;
+   case IMX_SRC_SRSR_WDOG3_RESET: /* FALLTHROUGH */
+   case IMX_SRC_SRSR_WDOG4_RESET: /* FALLTHROUGH */
+   case IMX_SRC_SRSR_WDOG1_RESET:
+   type = RESET_WDG;
+   break;
+   case IMX_SRC_SRSR_JTAG_RESET: /* FALLTHROUGH */
+   case IMX_SRC_SRSR_JTAG_SW_RESET:
+   type = RESET_JTAG;
+   break;
+   case IMX_SRC_SRSR_TEMPSENSE_RESET:
+   type = RESET_THERM;
+   break;
+   case IMX_SRC_SRSR_WARM_BOOT:
+   type = RESET_RST;
+   break;
+   }
+
+   reset_source_set(type);
+
+   switch (reg) {
+   case IMX_SRC_SRSR_WDOG3_RESET:
+   reset_source_set_instance(type, 1);
+   break;
+   case IMX_SRC_SRSR_WDOG4_RESET:
+   reset_source_set_instance(type, 2);
+   break;
+   }
+}
diff --git a/arch/arm/mach-imx/include/mach/reset-reason.h 
b/arch/arm/mach-imx/include/mach/reset-reason.h
new file mode 100644
index 0..96b905303
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/reset-reason.h
@@ -0,0 +1,17 @@
+#ifndef __MACH_RESET_REASON_H__
+#define __MACH_RESET_REASON_H__
+
+#define IMX_SRC_SRSR_IPP_RESET BIT(0)
+#define IMX_SRC_SRSR_CSU_RESET BIT(1)
+#define IMX_SRC_SRSR_IPP_USER_RESETBIT(3)
+#define IMX_SRC_SRSR_WDOG1_RESET   BIT(4)
+#define IMX_SRC_SRSR_JTAG_RESETBIT(5)
+#define IMX_SRC_SRSR_JTAG_SW_RESET BIT(6)
+#define IMX_SRC_SRSR_WDOG3_RESET   BIT(7)
+#define IMX_SRC_SRSR_WDOG4_RESET   BIT(8)
+#define IMX_SRC_SRSR_TEMPSENSE_RESET   BIT(9)
+#define IMX_SRC_SRSR_WARM_BOOT BIT(16)
+
+void imx_set_reset_reason(void __iomem *srsr);
+
+#endif /* __MACH_RESET_REASON_H__ */
-- 
2.14.3


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