subject:"Re\: \[RFC v4 01\/10\] Add initial RISC\-V architecture support"

Re: [RFC v4 01/10] Add initial RISC-V architecture support

2017-10-06 Thread Antony Pavlov

On Thu, 5 Oct 2017 12:55:09 +0200
Daniel Schultz  wrote:

> Hi,
> 
> On 10/03/2017 12:21 AM, Antony Pavlov wrote:
> > On Mon, 2 Oct 2017 12:08:58 +0200
> > Daniel Schultz  wrote:
> >
> >> Hi,
> >>
> >>
> >> On 09/29/2017 02:07 PM, Oleksij Rempel wrote:
> >>> Hi,
> >>>
> >>> hm... mostly looks identical with existing arch
> >>>
> >>> Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
>  Signed-off-by: Antony Pavlov 
>  --
>  TODOs:
> 
>  * split patch;
>  ---
> arch/riscv/Kconfig   | 73 
>  +
> arch/riscv/Makefile  | 68 +++
> arch/riscv/boot/Makefile |  2 +
> arch/riscv/boot/main_entry.c | 40 
> arch/riscv/boot/start.S  | 74 
>  ++
> arch/riscv/dts/.gitignore|  >  arch/riscv/dts/Makefile
>    |  9 
> arch/riscv/dts/skeleton.dtsi | 13 ++
> arch/riscv/include/asm/barebox.h |  1 +
> arch/riscv/include/asm/bitops.h  | 35 ++
> arch/riscv/include/asm/bitsperlong.h | 10 
> arch/riscv/include/asm/byteorder.h   | 10 
> arch/riscv/include/asm/common.h  |  6 +++
> arch/riscv/include/asm/elf.h | 11 +
> arch/riscv/include/asm/io.h  |  8 
> arch/riscv/include/asm/mmu.h |  6 +++
> arch/riscv/include/asm/posix_types.h |  1 +
> arch/riscv/include/asm/sections.h|  1 +
> arch/riscv/include/asm/string.h  |  1 +
> arch/riscv/include/asm/swab.h|  6 +++
> arch/riscv/include/asm/types.h   | 60 
> arch/riscv/include/asm/unaligned.h   | 19 
> arch/riscv/lib/.gitignore|  1 +
> arch/riscv/lib/Makefile  |  9 
> arch/riscv/lib/ashldi3.c | 28 
> arch/riscv/lib/ashrdi3.c | 30 
> arch/riscv/lib/asm-offsets.c | 12 +
> arch/riscv/lib/barebox.lds.S | 89 
>  
> arch/riscv/lib/dtb.c | 41 +
> arch/riscv/lib/libgcc.h  | 29 
> arch/riscv/lib/lshrdi3.c | 28 
> arch/riscv/lib/riscv_timer.c | 68 +++
> drivers/of/Kconfig   |  2 +-
> 33 files changed, 791 insertions(+), 1 deletion(-)
> 
>  diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>  new file mode 100644
>  index 0..b2f0817ef
>  --- /dev/null
>  +++ b/arch/riscv/Kconfig
>  @@ -0,0 +1,73 @@
>  +config RISCV
>  +bool
>  +select GENERIC_FIND_NEXT_BIT
>  +select HAVE_CONFIGURABLE_MEMORY_LAYOUT
>  +select HAVE_CONFIGURABLE_TEXT_BASE
>  +select GPIOLIB
>  +select OFTREE
>  +select COMMON_CLK
>  +select COMMON_CLK_OF_PROVIDER
>  +select CLKDEV_LOOKUP
>  +default y
>  +
>  +config ARCH_TEXT_BASE
>  +hex
>  +default 0x0
>  +
>  +config GENERIC_LINKER_SCRIPT
>  +bool
>  +default y
>  +
>  +menu "Machine selection"
>  +
>  +choice
>  +prompt "CPU selection"
>  +default CPU_RV_GENERIC
>  +
>  +config CPU_RV_GENERIC
>  +bool "Generic RISC-V"
>  +select CPU_SUPPORTS_32BIT_KERNEL
>  +select CPU_SUPPORTS_64BIT_KERNEL
>  +
>  +endchoice
>  +
>  +config CPU_SUPPORTS_32BIT_KERNEL
>  +bool
>  +config CPU_SUPPORTS_64BIT_KERNEL
>  +bool
>  +
>  +choice
>  +prompt "barebox code model"
>  +default 64BIT
>  +
>  +config 32BIT
>  +bool "32-bit barebox"
>  +depends on CPU_SUPPORTS_32BIT_KERNEL
>  +help
>  +  Select this option to build a 32-bit barebox.
>  +
>  +config 64BIT
>  +bool "64-bit barebox"
>  +depends on CPU_SUPPORTS_64BIT_KERNEL
>  +help
>  +  Select this option to build a 64-bit barebox.
>  +
>  +endchoice
>  +
>  +config BUILTIN_DTB
>  +bool "link a DTB into the barebox image"
>  +depends on OFTREE
>  +
>  +config BUILTIN_DTB_NAME
>  +string "DTB to build into the barebox image"
>  +depends on BUILTIN_DTB
>  +
>  +endmenu
>  +
>  +source common/Kconfig
>  +source commands/Kconfig
>  +source net/Kconfig
>  +source drivers/Kconfig
>  +source fs/Kconfig
>  +source lib/Kconfig
>

Re: [RFC v4 01/10] Add initial RISC-V architecture support

2017-10-05 Thread Daniel Schultz


Hi,

On 10/03/2017 12:21 AM, Antony Pavlov wrote:

On Mon, 2 Oct 2017 12:08:58 +0200
Daniel Schultz  wrote:


Hi,


On 09/29/2017 02:07 PM, Oleksij Rempel wrote:

Hi,

hm... mostly looks identical with existing arch

Am 29.09.2017 um 01:12 schrieb Antony Pavlov:

Signed-off-by: Antony Pavlov 
--
TODOs:

* split patch;
---
   arch/riscv/Kconfig   | 73 +
   arch/riscv/Makefile  | 68 +++
   arch/riscv/boot/Makefile |  2 +
   arch/riscv/boot/main_entry.c | 40 
   arch/riscv/boot/start.S  | 74 ++
   arch/riscv/dts/.gitignore|  >  arch/riscv/dts/Makefile   
   |  9 
   arch/riscv/dts/skeleton.dtsi | 13 ++
   arch/riscv/include/asm/barebox.h |  1 +
   arch/riscv/include/asm/bitops.h  | 35 ++
   arch/riscv/include/asm/bitsperlong.h | 10 
   arch/riscv/include/asm/byteorder.h   | 10 
   arch/riscv/include/asm/common.h  |  6 +++
   arch/riscv/include/asm/elf.h | 11 +
   arch/riscv/include/asm/io.h  |  8 
   arch/riscv/include/asm/mmu.h |  6 +++
   arch/riscv/include/asm/posix_types.h |  1 +
   arch/riscv/include/asm/sections.h|  1 +
   arch/riscv/include/asm/string.h  |  1 +
   arch/riscv/include/asm/swab.h|  6 +++
   arch/riscv/include/asm/types.h   | 60 
   arch/riscv/include/asm/unaligned.h   | 19 
   arch/riscv/lib/.gitignore|  1 +
   arch/riscv/lib/Makefile  |  9 
   arch/riscv/lib/ashldi3.c | 28 
   arch/riscv/lib/ashrdi3.c | 30 
   arch/riscv/lib/asm-offsets.c | 12 +
   arch/riscv/lib/barebox.lds.S | 89 

   arch/riscv/lib/dtb.c | 41 +
   arch/riscv/lib/libgcc.h  | 29 
   arch/riscv/lib/lshrdi3.c | 28 
   arch/riscv/lib/riscv_timer.c | 68 +++
   drivers/of/Kconfig   |  2 +-
   33 files changed, 791 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
new file mode 100644
index 0..b2f0817ef
--- /dev/null
+++ b/arch/riscv/Kconfig
@@ -0,0 +1,73 @@
+config RISCV
+   bool
+   select GENERIC_FIND_NEXT_BIT
+   select HAVE_CONFIGURABLE_MEMORY_LAYOUT
+   select HAVE_CONFIGURABLE_TEXT_BASE
+   select GPIOLIB
+   select OFTREE
+   select COMMON_CLK
+   select COMMON_CLK_OF_PROVIDER
+   select CLKDEV_LOOKUP
+   default y
+
+config ARCH_TEXT_BASE
+   hex
+   default 0x0
+
+config GENERIC_LINKER_SCRIPT
+   bool
+   default y
+
+menu "Machine selection"
+
+choice
+   prompt "CPU selection"
+   default CPU_RV_GENERIC
+
+config CPU_RV_GENERIC
+   bool "Generic RISC-V"
+   select CPU_SUPPORTS_32BIT_KERNEL
+   select CPU_SUPPORTS_64BIT_KERNEL
+
+endchoice
+
+config CPU_SUPPORTS_32BIT_KERNEL
+   bool
+config CPU_SUPPORTS_64BIT_KERNEL
+   bool
+
+choice
+   prompt "barebox code model"
+   default 64BIT
+
+config 32BIT
+   bool "32-bit barebox"
+   depends on CPU_SUPPORTS_32BIT_KERNEL
+   help
+ Select this option to build a 32-bit barebox.
+
+config 64BIT
+   bool "64-bit barebox"
+   depends on CPU_SUPPORTS_64BIT_KERNEL
+   help
+ Select this option to build a 64-bit barebox.
+
+endchoice
+
+config BUILTIN_DTB
+   bool "link a DTB into the barebox image"
+   depends on OFTREE
+
+config BUILTIN_DTB_NAME
+   string "DTB to build into the barebox image"
+   depends on BUILTIN_DTB
+
+endmenu
+
+source common/Kconfig
+source commands/Kconfig
+source net/Kconfig
+source drivers/Kconfig
+source fs/Kconfig
+source lib/Kconfig
+source crypto/Kconfig
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
new file mode 100644
index 0..4e3318cf1
--- /dev/null
+++ b/arch/riscv/Makefile
@@ -0,0 +1,68 @@
+CPPFLAGS += -fno-strict-aliasing
+
+cflags-y += -fno-pic -pipe
+cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \
+   -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany
+
+LDFLAGS += $(ldflags-y)
+LDFLAGS_barebox += -nostdlib
+
+TEXT_BASE = $(CONFIG_TEXT_BASE)
+CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
+
+ifndef CONFIG_MODULES
+# Add cleanup flags
+CPPFLAGS += -fdata-sections -ffunction-sections
+LDFLAGS_barebox += -static --gc-sections
+endif
+
+KBUILD_BINARY := barebox.bin
+
+machdirs := $(patsubst %,arch/riscv/mach-%/,$(machine-y))
+
+ifneq ($(board-y),)
+BOARD := arch/riscv/boards/$(board-y)/
+else
+BOARD :=
+endif
+
+ifeq ($(KBUILD_SRC),)
+CPPFLAGS += -I$(BOARD)/include
+else
+CPPFLAGS += -I$(srctree)/$(BOARD)/include
+endif
+
+ifeq ($(KBUILD_SRC),)
+CPPFLAGS += $(patsubst %,-I%include,$(machdirs))
+else

Re: [RFC v4 01/10] Add initial RISC-V architecture support

2017-10-02 Thread Antony Pavlov

On Mon, 2 Oct 2017 12:08:58 +0200
Daniel Schultz  wrote:

> Hi,
> 
> 
> On 09/29/2017 02:07 PM, Oleksij Rempel wrote:
> > Hi,
> >
> > hm... mostly looks identical with existing arch
> >
> > Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
> >> Signed-off-by: Antony Pavlov 
> >> --
> >> TODOs:
> >>
> >>* split patch;
> >> ---
> >>   arch/riscv/Kconfig   | 73 +
> >>   arch/riscv/Makefile  | 68 +++
> >>   arch/riscv/boot/Makefile |  2 +
> >>   arch/riscv/boot/main_entry.c | 40 
> >>   arch/riscv/boot/start.S  | 74 ++
> >>   arch/riscv/dts/.gitignore|  >  arch/riscv/dts/Makefile   
> >>|  9 
> >>   arch/riscv/dts/skeleton.dtsi | 13 ++
> >>   arch/riscv/include/asm/barebox.h |  1 +
> >>   arch/riscv/include/asm/bitops.h  | 35 ++
> >>   arch/riscv/include/asm/bitsperlong.h | 10 
> >>   arch/riscv/include/asm/byteorder.h   | 10 
> >>   arch/riscv/include/asm/common.h  |  6 +++
> >>   arch/riscv/include/asm/elf.h | 11 +
> >>   arch/riscv/include/asm/io.h  |  8 
> >>   arch/riscv/include/asm/mmu.h |  6 +++
> >>   arch/riscv/include/asm/posix_types.h |  1 +
> >>   arch/riscv/include/asm/sections.h|  1 +
> >>   arch/riscv/include/asm/string.h  |  1 +
> >>   arch/riscv/include/asm/swab.h|  6 +++
> >>   arch/riscv/include/asm/types.h   | 60 
> >>   arch/riscv/include/asm/unaligned.h   | 19 
> >>   arch/riscv/lib/.gitignore|  1 +
> >>   arch/riscv/lib/Makefile  |  9 
> >>   arch/riscv/lib/ashldi3.c | 28 
> >>   arch/riscv/lib/ashrdi3.c | 30 
> >>   arch/riscv/lib/asm-offsets.c | 12 +
> >>   arch/riscv/lib/barebox.lds.S | 89 
> >> 
> >>   arch/riscv/lib/dtb.c | 41 +
> >>   arch/riscv/lib/libgcc.h  | 29 
> >>   arch/riscv/lib/lshrdi3.c | 28 
> >>   arch/riscv/lib/riscv_timer.c | 68 +++
> >>   drivers/of/Kconfig   |  2 +-
> >>   33 files changed, 791 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >> new file mode 100644
> >> index 0..b2f0817ef
> >> --- /dev/null
> >> +++ b/arch/riscv/Kconfig
> >> @@ -0,0 +1,73 @@
> >> +config RISCV
> >> +  bool
> >> +  select GENERIC_FIND_NEXT_BIT
> >> +  select HAVE_CONFIGURABLE_MEMORY_LAYOUT
> >> +  select HAVE_CONFIGURABLE_TEXT_BASE
> >> +  select GPIOLIB
> >> +  select OFTREE
> >> +  select COMMON_CLK
> >> +  select COMMON_CLK_OF_PROVIDER
> >> +  select CLKDEV_LOOKUP
> >> +  default y
> >> +
> >> +config ARCH_TEXT_BASE
> >> +  hex
> >> +  default 0x0
> >> +
> >> +config GENERIC_LINKER_SCRIPT
> >> +  bool
> >> +  default y
> >> +
> >> +menu "Machine selection"
> >> +
> >> +choice
> >> +  prompt "CPU selection"
> >> +  default CPU_RV_GENERIC
> >> +
> >> +config CPU_RV_GENERIC
> >> +  bool "Generic RISC-V"
> >> +  select CPU_SUPPORTS_32BIT_KERNEL
> >> +  select CPU_SUPPORTS_64BIT_KERNEL
> >> +
> >> +endchoice
> >> +
> >> +config CPU_SUPPORTS_32BIT_KERNEL
> >> +  bool
> >> +config CPU_SUPPORTS_64BIT_KERNEL
> >> +  bool
> >> +
> >> +choice
> >> +  prompt "barebox code model"
> >> +  default 64BIT
> >> +
> >> +config 32BIT
> >> +  bool "32-bit barebox"
> >> +  depends on CPU_SUPPORTS_32BIT_KERNEL
> >> +  help
> >> +Select this option to build a 32-bit barebox.
> >> +
> >> +config 64BIT
> >> +  bool "64-bit barebox"
> >> +  depends on CPU_SUPPORTS_64BIT_KERNEL
> >> +  help
> >> +Select this option to build a 64-bit barebox.
> >> +
> >> +endchoice
> >> +
> >> +config BUILTIN_DTB
> >> +  bool "link a DTB into the barebox image"
> >> +  depends on OFTREE
> >> +
> >> +config BUILTIN_DTB_NAME
> >> +  string "DTB to build into the barebox image"
> >> +  depends on BUILTIN_DTB
> >> +
> >> +endmenu
> >> +
> >> +source common/Kconfig
> >> +source commands/Kconfig
> >> +source net/Kconfig
> >> +source drivers/Kconfig
> >> +source fs/Kconfig
> >> +source lib/Kconfig
> >> +source crypto/Kconfig
> >> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> >> new file mode 100644
> >> index 0..4e3318cf1
> >> --- /dev/null
> >> +++ b/arch/riscv/Makefile
> >> @@ -0,0 +1,68 @@
> >> +CPPFLAGS += -fno-strict-aliasing
> >> +
> >> +cflags-y += -fno-pic -pipe
> >> +cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \
> >> +  -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany
> >> +
> >> +LDFLAGS += $(ldflags-y)
> >> +LDFLAGS_barebox += -nostdlib
> >> +
> >> +TEXT_BASE = $(CONFIG_TEXT_BASE)
> >> +CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
> >> +
> >> +ifndef CONFIG_MODULES
> >> +# Add cleanup flags
> >> +CPPFLAGS +=

Re: [RFC v4 01/10] Add initial RISC-V architecture support

2017-10-02 Thread Antony Pavlov

On Mon, 2 Oct 2017 12:04:30 +0200
Daniel Schultz  wrote:

> Hi,
> 
> 
> On 09/30/2017 01:57 PM, Antony Pavlov wrote:
> > On Fri, 29 Sep 2017 14:07:09 +0200
> > Oleksij Rempel  wrote:
> >
> >> Hi,
> >>
> >> hm... mostly looks identical with existing arch
> > What do you mean when you say "existing arch"?
> >
> > ...
> >
> >> Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
> > ...
> >>> diff --git a/arch/riscv/boot/start.S b/arch/riscv/boot/start.S
> >>> new file mode 100644
> >>> index 0..2fd00f63d
> >>> --- /dev/null
> >>> +++ b/arch/riscv/boot/start.S
> >>> @@ -0,0 +1,74 @@
> >>> +/*
> >>> + * Startup Code for MIPS CPU
> >>> + *
> >>> + * based on coreboot/src/arch/riscv/bootblock.S
> >>> + *
> >>> + * Copyright (C) 2016 Antony Pavlov 
> >>> + *
> >>> + * This file is part of barebox.
> >>> + * See file CREDITS for list of people who contributed to this project.
> >>> + *
> >>> + * This program is free software; you can redistribute it and/or modify
> >>> + * it under the terms of the GNU General Public License version 2
> >>> + * as published by the Free Software Foundation.
> >>> + *
> >>> + * This program is distributed in the hope that it will be useful,
> >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>> + * GNU General Public License for more details.
> >>> + *
> >>> + */
> >>> +
> >>> +#include 
> >>> +
> >>> + .text
> >>> + .section ".text_entry"
> >>> + .align 2
> >>> +
> >>> +.globl _start
> >>> +_start:
> >>> + li sp, STACK_BASE + STACK_SIZE
> >>> +
> >>> + # make room for HLS and initialize it
> >>> + addi sp, sp, -64 /* MENTRY_FRAME_SIZE */
> >>> +
> >>> + # poison the stack
> >>> + li t1, STACK_BASE
> >>> + li t0, 0xdeadbeef
> >>> + sw t0, 0(t1)
> >>> +
> >>> + # clear any pending interrupts
> >>> + //csrwi mip, 0
> >> should be removed.
> > Actually not!
> >
> > I have imported this code from coreboot.
> >
> > I have commented this line because csrwi does not worked in some cases.
> >
> > But I have to make additional investigations on csrwi.
> >
> CSRRWI is part of the base integer instruction set and the machine mode 
> is mandatory. If there are troubles with this instruction, the core has 
> a faulty design. So executing this line should be okay even if there is 
> no interrupt controller.
> 

It's not a bug, it's a feature :)

At the moment I use picorv32 core.

Here is a quote from 
https://github.com/cliffordwolf/picorv32#custom-instructions-for-irq-handling

 The IRQ handling features in PicoRV32 do not follow the RISC-V Privileged 
ISA specification.
 Instead a small set of very simple custom instructions is used to 
implement IRQ handling with
 minimal hardware overhead.

I'm planning to make it possible to use another core instead of picorv32 in 
Eriso SoC,
so I can introduce something like SYS_HAS_PICORV32_CPU Kconfig macro.

> -- 
> Mit freundlichen Grüßen,
> With best regards,
>Daniel Schultz
> 
> 
> ___
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox


-- 
Best regards,
  Antony Pavlov

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Re: [RFC v4 01/10] Add initial RISC-V architecture support

2017-10-02 Thread Antony Pavlov

On Mon, 2 Oct 2017 09:43:02 +0200
Oleksij Rempel  wrote:

> Hi,
> 
> Am 30.09.2017 um 13:57 schrieb Antony Pavlov:
> > On Fri, 29 Sep 2017 14:07:09 +0200
> > Oleksij Rempel  wrote:
> > 
> >> Hi,
> >>
> >> hm... mostly looks identical with existing arch
> > 
> > What do you mean when you say "existing arch"?
> 
> it is a note for me. I just compared it with MIPS
> > ...
> > 
> >> Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
> > ...
> >>> diff --git a/arch/riscv/boot/start.S b/arch/riscv/boot/start.S
> >>> new file mode 100644
> >>> index 0..2fd00f63d
> >>> --- /dev/null
> >>> +++ b/arch/riscv/boot/start.S
> >>> @@ -0,0 +1,74 @@
> >>> +/*
> >>> + * Startup Code for MIPS CPU
> 
> Beside here is a copy paste ^^^ artefact :)

Thanks! I have just fixed this.

> 
> >>> + * based on coreboot/src/arch/riscv/bootblock.S
> >>> + *
> >>> + * Copyright (C) 2016 Antony Pavlov 
> >>> + *

-- 
Best regards,
  Antony Pavlov

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Re: [RFC v4 01/10] Add initial RISC-V architecture support

2017-10-02 Thread Daniel Schultz


Hi,


On 09/29/2017 02:07 PM, Oleksij Rempel wrote:

Hi,

hm... mostly looks identical with existing arch

Am 29.09.2017 um 01:12 schrieb Antony Pavlov:

Signed-off-by: Antony Pavlov 
--
TODOs:

   * split patch;
---
  arch/riscv/Kconfig   | 73 +
  arch/riscv/Makefile  | 68 +++
  arch/riscv/boot/Makefile |  2 +
  arch/riscv/boot/main_entry.c | 40 
  arch/riscv/boot/start.S  | 74 ++
  arch/riscv/dts/.gitignore|  >  arch/riscv/dts/Makefile
  |  9 
  arch/riscv/dts/skeleton.dtsi | 13 ++
  arch/riscv/include/asm/barebox.h |  1 +
  arch/riscv/include/asm/bitops.h  | 35 ++
  arch/riscv/include/asm/bitsperlong.h | 10 
  arch/riscv/include/asm/byteorder.h   | 10 
  arch/riscv/include/asm/common.h  |  6 +++
  arch/riscv/include/asm/elf.h | 11 +
  arch/riscv/include/asm/io.h  |  8 
  arch/riscv/include/asm/mmu.h |  6 +++
  arch/riscv/include/asm/posix_types.h |  1 +
  arch/riscv/include/asm/sections.h|  1 +
  arch/riscv/include/asm/string.h  |  1 +
  arch/riscv/include/asm/swab.h|  6 +++
  arch/riscv/include/asm/types.h   | 60 
  arch/riscv/include/asm/unaligned.h   | 19 
  arch/riscv/lib/.gitignore|  1 +
  arch/riscv/lib/Makefile  |  9 
  arch/riscv/lib/ashldi3.c | 28 
  arch/riscv/lib/ashrdi3.c | 30 
  arch/riscv/lib/asm-offsets.c | 12 +
  arch/riscv/lib/barebox.lds.S | 89 
  arch/riscv/lib/dtb.c | 41 +
  arch/riscv/lib/libgcc.h  | 29 
  arch/riscv/lib/lshrdi3.c | 28 
  arch/riscv/lib/riscv_timer.c | 68 +++
  drivers/of/Kconfig   |  2 +-
  33 files changed, 791 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
new file mode 100644
index 0..b2f0817ef
--- /dev/null
+++ b/arch/riscv/Kconfig
@@ -0,0 +1,73 @@
+config RISCV
+   bool
+   select GENERIC_FIND_NEXT_BIT
+   select HAVE_CONFIGURABLE_MEMORY_LAYOUT
+   select HAVE_CONFIGURABLE_TEXT_BASE
+   select GPIOLIB
+   select OFTREE
+   select COMMON_CLK
+   select COMMON_CLK_OF_PROVIDER
+   select CLKDEV_LOOKUP
+   default y
+
+config ARCH_TEXT_BASE
+   hex
+   default 0x0
+
+config GENERIC_LINKER_SCRIPT
+   bool
+   default y
+
+menu "Machine selection"
+
+choice
+   prompt "CPU selection"
+   default CPU_RV_GENERIC
+
+config CPU_RV_GENERIC
+   bool "Generic RISC-V"
+   select CPU_SUPPORTS_32BIT_KERNEL
+   select CPU_SUPPORTS_64BIT_KERNEL
+
+endchoice
+
+config CPU_SUPPORTS_32BIT_KERNEL
+   bool
+config CPU_SUPPORTS_64BIT_KERNEL
+   bool
+
+choice
+   prompt "barebox code model"
+   default 64BIT
+
+config 32BIT
+   bool "32-bit barebox"
+   depends on CPU_SUPPORTS_32BIT_KERNEL
+   help
+ Select this option to build a 32-bit barebox.
+
+config 64BIT
+   bool "64-bit barebox"
+   depends on CPU_SUPPORTS_64BIT_KERNEL
+   help
+ Select this option to build a 64-bit barebox.
+
+endchoice
+
+config BUILTIN_DTB
+   bool "link a DTB into the barebox image"
+   depends on OFTREE
+
+config BUILTIN_DTB_NAME
+   string "DTB to build into the barebox image"
+   depends on BUILTIN_DTB
+
+endmenu
+
+source common/Kconfig
+source commands/Kconfig
+source net/Kconfig
+source drivers/Kconfig
+source fs/Kconfig
+source lib/Kconfig
+source crypto/Kconfig
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
new file mode 100644
index 0..4e3318cf1
--- /dev/null
+++ b/arch/riscv/Makefile
@@ -0,0 +1,68 @@
+CPPFLAGS += -fno-strict-aliasing
+
+cflags-y += -fno-pic -pipe
+cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \
+   -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany
+
+LDFLAGS += $(ldflags-y)
+LDFLAGS_barebox += -nostdlib
+
+TEXT_BASE = $(CONFIG_TEXT_BASE)
+CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
+
+ifndef CONFIG_MODULES
+# Add cleanup flags
+CPPFLAGS += -fdata-sections -ffunction-sections
+LDFLAGS_barebox += -static --gc-sections
+endif
+
+KBUILD_BINARY := barebox.bin
+
+machdirs := $(patsubst %,arch/riscv/mach-%/,$(machine-y))
+
+ifneq ($(board-y),)
+BOARD := arch/riscv/boards/$(board-y)/
+else
+BOARD :=
+endif
+
+ifeq ($(KBUILD_SRC),)
+CPPFLAGS += -I$(BOARD)/include
+else
+CPPFLAGS += -I$(srctree)/$(BOARD)/include
+endif
+
+ifeq ($(KBUILD_SRC),)
+CPPFLAGS += $(patsubst %,-I%include,$(machdirs))
+else
+CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
+endif
+
+archprepare: maketools
+
+PHONY += maketools
+
+ifneq ($(machine-y),)
+MACH  :=

Re: [RFC v4 01/10] Add initial RISC-V architecture support

2017-10-02 Thread Daniel Schultz


Hi,


On 09/30/2017 01:57 PM, Antony Pavlov wrote:

On Fri, 29 Sep 2017 14:07:09 +0200
Oleksij Rempel  wrote:


Hi,

hm... mostly looks identical with existing arch

What do you mean when you say "existing arch"?

...


Am 29.09.2017 um 01:12 schrieb Antony Pavlov:

...

diff --git a/arch/riscv/boot/start.S b/arch/riscv/boot/start.S
new file mode 100644
index 0..2fd00f63d
--- /dev/null
+++ b/arch/riscv/boot/start.S
@@ -0,0 +1,74 @@
+/*
+ * Startup Code for MIPS CPU
+ *
+ * based on coreboot/src/arch/riscv/bootblock.S
+ *
+ * Copyright (C) 2016 Antony Pavlov 
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include 
+
+   .text
+   .section ".text_entry"
+   .align 2
+
+.globl _start
+_start:
+   li sp, STACK_BASE + STACK_SIZE
+
+   # make room for HLS and initialize it
+   addi sp, sp, -64 /* MENTRY_FRAME_SIZE */
+
+   # poison the stack
+   li t1, STACK_BASE
+   li t0, 0xdeadbeef
+   sw t0, 0(t1)
+
+   # clear any pending interrupts
+   //csrwi mip, 0

should be removed.

Actually not!

I have imported this code from coreboot.

I have commented this line because csrwi does not worked in some cases.

But I have to make additional investigations on csrwi.

CSRRWI is part of the base integer instruction set and the machine mode 
is mandatory. If there are troubles with this instruction, the core has 
a faulty design. So executing this line should be okay even if there is 
no interrupt controller.


--
Mit freundlichen Grüßen,
With best regards,
  Daniel Schultz


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Re: [RFC v4 01/10] Add initial RISC-V architecture support

2017-10-02 Thread Oleksij Rempel

Hi,

Am 30.09.2017 um 13:57 schrieb Antony Pavlov:
> On Fri, 29 Sep 2017 14:07:09 +0200
> Oleksij Rempel  wrote:
> 
>> Hi,
>>
>> hm... mostly looks identical with existing arch
> 
> What do you mean when you say "existing arch"?

it is a note for me. I just compared it with MIPS
> ...
> 
>> Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
> ...
>>> diff --git a/arch/riscv/boot/start.S b/arch/riscv/boot/start.S
>>> new file mode 100644
>>> index 0..2fd00f63d
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/start.S
>>> @@ -0,0 +1,74 @@
>>> +/*
>>> + * Startup Code for MIPS CPU

Beside here is a copy paste ^^^ artefact :)

>>> + * based on coreboot/src/arch/riscv/bootblock.S
>>> + *
>>> + * Copyright (C) 2016 Antony Pavlov 
>>> + *

-- 
Regards,
Oleksij



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Re: [RFC v4 01/10] Add initial RISC-V architecture support

2017-09-30 Thread Antony Pavlov

On Fri, 29 Sep 2017 14:07:09 +0200
Oleksij Rempel  wrote:

> Hi,
> 
> hm... mostly looks identical with existing arch

What do you mean when you say "existing arch"?

...

> Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
...
> > diff --git a/arch/riscv/boot/start.S b/arch/riscv/boot/start.S
> > new file mode 100644
> > index 0..2fd00f63d
> > --- /dev/null
> > +++ b/arch/riscv/boot/start.S
> > @@ -0,0 +1,74 @@
> > +/*
> > + * Startup Code for MIPS CPU
> > + *
> > + * based on coreboot/src/arch/riscv/bootblock.S
> > + *
> > + * Copyright (C) 2016 Antony Pavlov 
> > + *
> > + * This file is part of barebox.
> > + * See file CREDITS for list of people who contributed to this project.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2
> > + * as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + */
> > +
> > +#include 
> > +
> > +   .text
> > +   .section ".text_entry"
> > +   .align 2
> > +
> > +.globl _start
> > +_start:
> > +   li sp, STACK_BASE + STACK_SIZE
> > +
> > +   # make room for HLS and initialize it
> > +   addi sp, sp, -64 /* MENTRY_FRAME_SIZE */
> > +
> > +   # poison the stack
> > +   li t1, STACK_BASE
> > +   li t0, 0xdeadbeef
> > +   sw t0, 0(t1)
> > +
> > +   # clear any pending interrupts
> > +   //csrwi mip, 0
> 
> should be removed.

Actually not!

I have imported this code from coreboot.

I have commented this line because csrwi does not worked in some cases.

But I have to make additional investigations on csrwi.

> 
> > +   /* copy barebox to link location */
> > +
> > +   la  a0, _start  /* a0 <- _start actual address */
> > +   li  a1, CONFIG_TEXT_BASE/* a1 <- _start link address */
> > +
> > +   beq a0, a1, main_entry
> > +
> > +   la  a2, __bss_start
> > +
> > +#define LONGSIZE 4
> > +
> > +copy_loop:
> > +   /* copy from source address [a0] */
> > +   lw  t0, LONGSIZE * 0(a0)
> > +   lw  t1, LONGSIZE * 1(a0)
> > +   lw  t2, LONGSIZE * 2(a0)
> > +   lw  t3, LONGSIZE * 3(a0)
> > +   /* copy to target address [a1] */
> > +   sw  t0, LONGSIZE * 0(a1)
> > +   sw  t1, LONGSIZE * 1(a1)
> > +   sw  t2, LONGSIZE * 2(a1)
> > +   sw  t3, LONGSIZE * 3(a1)
> > +   addia0, a0, LONGSIZE * 2
> > +   addia1, a1, LONGSIZE * 2
> > +   bgeua2, a0, copy_loop
> > +
> > +   /* Alas! At the moment I can't load main_entry __link__ address
> > +  into a0 with la. Use CONFIG_TEXT_BASE instead. This solution
> > +  leads to extra cycles for repeat sp initialization. */
> > +
> > +   li  a0, CONFIG_TEXT_BASE
> > +   jalra0
> > diff --git a/arch/riscv/dts/.gitignore b/arch/riscv/dts/.gitignore
> > new file mode 100644
> > index 0..077903c50
> > --- /dev/null
> > +++ b/arch/riscv/dts/.gitignore
> > @@ -0,0 +1 @@
> > +*dtb*
> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> > new file mode 100644
> > index 0..f8380b11c
> > --- /dev/null
> > +++ b/arch/riscv/dts/Makefile
> > @@ -0,0 +1,9 @@
> > +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
> > +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
> > +
> > +# just to build a built-in.o. Otherwise compilation fails when no 
> > devicetree is
> > +# created.
> > +obj- += dummy.o
> > +
> > +always := $(dtb-y)
> > +clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts
> > diff --git a/arch/riscv/dts/skeleton.dtsi b/arch/riscv/dts/skeleton.dtsi
> > new file mode 100644
> > index 0..38ead821b
> > --- /dev/null
> > +++ b/arch/riscv/dts/skeleton.dtsi
> > @@ -0,0 +1,13 @@
> > +/*
> > + * Skeleton device tree; the bare minimum needed to boot; just include and
> > + * add a compatible value.  The bootloader will typically populate the 
> > memory
> > + * node.
> > + */
> > +
> > +/ {
> > +   #address-cells = <2>;
> > +   #size-cells = <1>;
> > +   chosen { };
> > +   aliases { };
> > +   memory { device_type = "memory"; reg = <0 0 0>; };
> 
> "reg = <0 0>" instead?

no.

We have

  #address-cells = <2>;
  #size-cells = <1>;

here.

-- 
Best regards,
  Antony Pavlov

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Re: [RFC v4 01/10] Add initial RISC-V architecture support

2017-09-29 Thread Oleksij Rempel

Hi,

hm... mostly looks identical with existing arch

Am 29.09.2017 um 01:12 schrieb Antony Pavlov:
> Signed-off-by: Antony Pavlov 
> --
> TODOs:
> 
>   * split patch;
> ---
>  arch/riscv/Kconfig   | 73 +
>  arch/riscv/Makefile  | 68 +++
>  arch/riscv/boot/Makefile |  2 +
>  arch/riscv/boot/main_entry.c | 40 
>  arch/riscv/boot/start.S  | 74 ++
>  arch/riscv/dts/.gitignore|  >  arch/riscv/dts/Makefile   
>|  9 
>  arch/riscv/dts/skeleton.dtsi | 13 ++
>  arch/riscv/include/asm/barebox.h |  1 +
>  arch/riscv/include/asm/bitops.h  | 35 ++
>  arch/riscv/include/asm/bitsperlong.h | 10 
>  arch/riscv/include/asm/byteorder.h   | 10 
>  arch/riscv/include/asm/common.h  |  6 +++
>  arch/riscv/include/asm/elf.h | 11 +
>  arch/riscv/include/asm/io.h  |  8 
>  arch/riscv/include/asm/mmu.h |  6 +++
>  arch/riscv/include/asm/posix_types.h |  1 +
>  arch/riscv/include/asm/sections.h|  1 +
>  arch/riscv/include/asm/string.h  |  1 +
>  arch/riscv/include/asm/swab.h|  6 +++
>  arch/riscv/include/asm/types.h   | 60 
>  arch/riscv/include/asm/unaligned.h   | 19 
>  arch/riscv/lib/.gitignore|  1 +
>  arch/riscv/lib/Makefile  |  9 
>  arch/riscv/lib/ashldi3.c | 28 
>  arch/riscv/lib/ashrdi3.c | 30 
>  arch/riscv/lib/asm-offsets.c | 12 +
>  arch/riscv/lib/barebox.lds.S | 89 
> 
>  arch/riscv/lib/dtb.c | 41 +
>  arch/riscv/lib/libgcc.h  | 29 
>  arch/riscv/lib/lshrdi3.c | 28 
>  arch/riscv/lib/riscv_timer.c | 68 +++
>  drivers/of/Kconfig   |  2 +-
>  33 files changed, 791 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> new file mode 100644
> index 0..b2f0817ef
> --- /dev/null
> +++ b/arch/riscv/Kconfig
> @@ -0,0 +1,73 @@
> +config RISCV
> + bool
> + select GENERIC_FIND_NEXT_BIT
> + select HAVE_CONFIGURABLE_MEMORY_LAYOUT
> + select HAVE_CONFIGURABLE_TEXT_BASE
> + select GPIOLIB
> + select OFTREE
> + select COMMON_CLK
> + select COMMON_CLK_OF_PROVIDER
> + select CLKDEV_LOOKUP
> + default y
> +
> +config ARCH_TEXT_BASE
> + hex
> + default 0x0
> +
> +config GENERIC_LINKER_SCRIPT
> + bool
> + default y
> +
> +menu "Machine selection"
> +
> +choice
> + prompt "CPU selection"
> + default CPU_RV_GENERIC
> +
> +config CPU_RV_GENERIC
> + bool "Generic RISC-V"
> + select CPU_SUPPORTS_32BIT_KERNEL
> + select CPU_SUPPORTS_64BIT_KERNEL
> +
> +endchoice
> +
> +config CPU_SUPPORTS_32BIT_KERNEL
> + bool
> +config CPU_SUPPORTS_64BIT_KERNEL
> + bool
> +
> +choice
> + prompt "barebox code model"
> + default 64BIT
> +
> +config 32BIT
> + bool "32-bit barebox"
> + depends on CPU_SUPPORTS_32BIT_KERNEL
> + help
> +   Select this option to build a 32-bit barebox.
> +
> +config 64BIT
> + bool "64-bit barebox"
> + depends on CPU_SUPPORTS_64BIT_KERNEL
> + help
> +   Select this option to build a 64-bit barebox.
> +
> +endchoice
> +
> +config BUILTIN_DTB
> + bool "link a DTB into the barebox image"
> + depends on OFTREE
> +
> +config BUILTIN_DTB_NAME
> + string "DTB to build into the barebox image"
> + depends on BUILTIN_DTB
> +
> +endmenu
> +
> +source common/Kconfig
> +source commands/Kconfig
> +source net/Kconfig
> +source drivers/Kconfig
> +source fs/Kconfig
> +source lib/Kconfig
> +source crypto/Kconfig
> diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
> new file mode 100644
> index 0..4e3318cf1
> --- /dev/null
> +++ b/arch/riscv/Makefile
> @@ -0,0 +1,68 @@
> +CPPFLAGS += -fno-strict-aliasing
> +
> +cflags-y += -fno-pic -pipe
> +cflags-y += -Wall -Wmissing-prototypes -Wstrict-prototypes \
> + -Wno-uninitialized -Wno-format -Wno-main -mcmodel=medany
> +
> +LDFLAGS += $(ldflags-y)
> +LDFLAGS_barebox += -nostdlib
> +
> +TEXT_BASE = $(CONFIG_TEXT_BASE)
> +CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE)
> +
> +ifndef CONFIG_MODULES
> +# Add cleanup flags
> +CPPFLAGS += -fdata-sections -ffunction-sections
> +LDFLAGS_barebox += -static --gc-sections
> +endif
> +
> +KBUILD_BINARY := barebox.bin
> +
> +machdirs := $(patsubst %,arch/riscv/mach-%/,$(machine-y))
> +
> +ifneq ($(board-y),)
> +BOARD := arch/riscv/boards/$(board-y)/
> +else
> +BOARD :=
> +endif
> +
> +ifeq ($(KBUILD_SRC),)
> +CPPFLAGS += -I$(BOARD)/include
> +else
> +CPPFLAGS += -I$(srctree)/$(BOARD)/include
> +endif
> +
> +ifeq ($(KBUILD_SRC),)
> +CPPFLAGS += $(patsubst %,-I%include,$(machdirs))
> +else
>

Re: [RFC v4 01/10] Add initial RISC-V architecture support

Re: [RFC v4 01/10] Add initial RISC-V architecture support

Re: [RFC v4 01/10] Add initial RISC-V architecture support

Re: [RFC v4 01/10] Add initial RISC-V architecture support

Re: [RFC v4 01/10] Add initial RISC-V architecture support

Re: [RFC v4 01/10] Add initial RISC-V architecture support

Re: [RFC v4 01/10] Add initial RISC-V architecture support

Re: [RFC v4 01/10] Add initial RISC-V architecture support

Re: [RFC v4 01/10] Add initial RISC-V architecture support

Re: [RFC v4 01/10] Add initial RISC-V architecture support

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