v2: correct the simd mode output SIMD8 instead of SIMD4*2
Signed-off-by: Guo Yejun
---
backend/src/backend/gen/gen_mesa_disasm.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/backend/src/backend/gen/gen_mesa_disasm.c
b/backend/src/backend/gen/gen_
the destination type is ud, not uw. Correct it to make the ASM more readable.
Signed-off-by: Guo Yejun
---
backend/src/backend/gen_encoder.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/backend/src/backend/gen_encoder.cpp
b/backend/src/backend/gen_encoder.cpp
index 9f9e
currently, the unaligned bytes gather is implemented with readByteAsDWord
for a good performance, change back to native byte scattered read
for new GPU generations with better performance.
as for vload16(1/2/.../15, global char*), the native byte scattered
read is not good, so use the original met
Once the byte scattered read with more than one byte is enabled,
there will same ir reg with different subnr, it makes the current
logic in SELECTION IR optmization (local copy propogation) incorrect,
so fix the issue by scanning all the map.
Signed-off-by: Guo Yejun
---
backend/src/backend/gen_
From: Yan Wang
Contributor: Junyan He
Signed-off-by: Yan Wang
---
backend/src/llvm/llvm_gen_backend.cpp | 95 +--
1 file changed, 80 insertions(+), 15 deletions(-)
diff --git a/backend/src/llvm/llvm_gen_backend.cpp
b/backend/src/llvm/llvm_gen_backend.cpp
index
Sorry. I have re-sent 7/12.
Yan Wang
> patch of 06 and 07 have the same title?
> I think it is a typo here.
> Please correct it.
> All the other things are OK, just rename this one and
> the whole patchset can be pushed later.
>
> Also can push my patch about printf test cases together.
>
> On Mo
patch of 06 and 07 have the same title?
I think it is a typo here.
Please correct it.
All the other things are OK, just rename this one and
the whole patchset can be pushed later.
Also can push my patch about printf test cases together.
On Mon, Feb 01, 2016 at 03:42:16PM +0800, yan.w...@linux.int