it is tricky that ir reg is UD but allocated as UW.
for this special case, header/tmp should be allocated with fixed size of
physical register, no matter of SIMD-n, how about to add a new FAMILY at ir
level for such special case.
-Original Message-
From: Beignet
Looks good. Thanks for the fix.
- Ruiling
> -Original Message-
> From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
> yan.w...@linux.intel.com
> Sent: Thursday, November 24, 2016 2:55 PM
> To: beignet@lists.freedesktop.org
> Cc: Yan Wang
From: Yan Wang
If it isn't initialized, Luxmark hotel scene will display wrong.
---
backend/src/backend/gen_insn_selection.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/backend/src/backend/gen_insn_selection.cpp
From: Yan Wang
If it isn't initialized, Luxmark hotel scene will display wrong.
---
backend/src/backend/gen_insn_selection.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/backend/src/backend/gen_insn_selection.cpp
From: Yan Wang
If it isn't initialized, Luxmark hotel scene will display wrong.
---
backend/src/backend/gen_insn_selection.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/backend/src/backend/gen_insn_selection.cpp
v2: use function setSendsOperands
Signed-off-by: Guo, Yejun
---
backend/src/backend/gen9_encoder.cpp | 48 ++
backend/src/backend/gen9_encoder.hpp | 2 ++
backend/src/backend/gen_context.cpp| 15 +++---
sends is a new instruction starting from gen9 to split the registers
of address and data for write, the register pressure can be loosed
since they are not necessary to be continuous any more.
more patches for sends will be sent out.
we can choose send or sends based on hasSends() in selection
v2: output dst register for sends
Signed-off-by: Guo, Yejun
---
backend/src/backend/gen/gen_mesa_disasm.c | 31 +++--
backend/src/backend/gen9_instruction.hpp | 112 ++
backend/src/backend/gen_defs.hpp | 3 +
3 files changed, 142
> + unsigned
> Gen9Encoder::setUntypedWriteSendsMessageDesc(GenNativeInstruction
> *insn, unsigned bti, unsigned elemNum)
The message desc encoding is same for send and sends, what about calling
existing function?
66 void Gen8Encoder::setDPUntypedRW(GenNativeInstruction *insn,
67
ok
-Original Message-
From: Song, Ruiling
Sent: Thursday, November 24, 2016 10:33 AM
To: Guo, Yejun; beignet@lists.freedesktop.org
Subject: RE: [Beignet] [PATCH 1/4] prepare gen9 sends binary format and enable
the ASM dump for sends
> -Original Message-
> From: Guo, Yejun
>
> -Original Message-
> From: Guo, Yejun
> Sent: Thursday, November 24, 2016 10:21 AM
> To: Song, Ruiling ; beignet@lists.freedesktop.org
> Subject: RE: [Beignet] [PATCH 1/4] prepare gen9 sends binary format and enable
> the ASM dump for sends
>
> thanks, and two
thanks, and two inline comments, right?
> +string(file, "null");
This is not a good idea. Please parse the instruction bits to know whether it
is the null register.
[yejun] yes, when I did something like atomic which has return value, I found
it is not always null. So, I fixed this in
> -Original Message-
> From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
> Guo, Yejun
> Sent: Tuesday, November 22, 2016 2:43 PM
> To: beignet@lists.freedesktop.org
> Cc: Guo, Yejun
> Subject: [Beignet] [PATCH 2/4] support sends (split send)
> -Original Message-
> From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
> Guo, Yejun
> Sent: Tuesday, November 22, 2016 2:42 PM
> To: beignet@lists.freedesktop.org
> Cc: Guo, Yejun
> Subject: [Beignet] [PATCH 1/4] prepare gen9 sends binary
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