from:"Mark Thompson"

[Beignet] [PATCH 3/3] Enable Coffee Lake support

2018-01-31 Thread Mark Thompson

Little change is needed here because the graphics core is the same as
Kaby Lake.  Includes all PCI IDs currently supported by the kernel driver
in the drm-intel tree (Coffee Lake S, H and U devices in GT 1, 2 and 3
configurations).

Signed-off-by: Mark Thompson <s...@jkqxz.net>
---
 backend/src/backend/gen_program.cpp |  5 ++
 src/cl_device_data.h| 54 -
 src/cl_device_id.c  | 97 -
 3 files changed, 153 insertions(+), 3 deletions(-)

diff --git a/backend/src/backend/gen_program.cpp 
b/backend/src/backend/gen_program.cpp
index e06ed40c..274c99c7 100644
--- a/backend/src/backend/gen_program.cpp
+++ b/backend/src/backend/gen_program.cpp
@@ -209,6 +209,8 @@ namespace gbe {
   ctx = GBE_NEW(BxtContext, unit, name, deviceID, relaxMath);
 } else if (IS_KABYLAKE(deviceID)) {
   ctx = GBE_NEW(KblContext, unit, name, deviceID, relaxMath);
+} else if (IS_COFFEELAKE(deviceID)) {
+  ctx = GBE_NEW(KblContext, unit, name, deviceID, relaxMath);
 } else if (IS_GEMINILAKE(deviceID)) {
   ctx = GBE_NEW(GlkContext, unit, name, deviceID, relaxMath);
 }
@@ -328,6 +330,7 @@ namespace gbe {
   (IS_SKYLAKE(deviceID) && 
MATCH_SKL_HEADER(binary)) || \
   (IS_BROXTON(deviceID) && 
MATCH_BXT_HEADER(binary)) || \
   (IS_KABYLAKE(deviceID) && 
MATCH_KBL_HEADER(binary)) || \
+  (IS_COFFEELAKE(deviceID) && 
MATCH_KBL_HEADER(binary)) || \
   (IS_GEMINILAKE(deviceID) && 
MATCH_GLK_HEADER(binary)) \
   )
 
@@ -436,6 +439,8 @@ namespace gbe {
 FILL_BXT_HEADER(*binary);
   }else if(IS_KABYLAKE(prog->deviceID)){
 FILL_KBL_HEADER(*binary);
+  }else if(IS_COFFEELAKE(prog->deviceID)){
+FILL_KBL_HEADER(*binary);
   }else if(IS_GEMINILAKE(prog->deviceID)){
 FILL_GLK_HEADER(*binary);
   }else {
diff --git a/src/cl_device_data.h b/src/cl_device_data.h
index 123b6192..79f7002e 100644
--- a/src/cl_device_data.h
+++ b/src/cl_device_data.h
@@ -372,7 +372,59 @@
   (devid == PCI_CHIP_GLK_3x6 ||   \
devid == PCI_CHIP_GLK_2x6)
 
-#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid) || 
IS_KABYLAKE(devid) || IS_GEMINILAKE(devid))
+#define PCI_CHIP_COFFEELAKE_S_GT1_1  0x3E90
+#define PCI_CHIP_COFFEELAKE_S_GT1_2  0x3E93
+#define PCI_CHIP_COFFEELAKE_S_GT1_3  0x3E99
+
+#define PCI_CHIP_COFFEELAKE_U_GT1_1  0x3EA1
+#define PCI_CHIP_COFFEELAKE_U_GT1_2  0x3EA4
+
+#define PCI_CHIP_COFFEELAKE_S_GT2_1  0x3E91
+#define PCI_CHIP_COFFEELAKE_S_GT2_2  0x3E92
+#define PCI_CHIP_COFFEELAKE_S_GT2_3  0x3E96
+#define PCI_CHIP_COFFEELAKE_S_GT2_4  0x3E9A
+
+#define PCI_CHIP_COFFEELAKE_H_GT2_1  0x3E94
+#define PCI_CHIP_COFFEELAKE_H_GT2_2  0x3E9B
+
+#define PCI_CHIP_COFFEELAKE_U_GT2_1  0x3EA0
+#define PCI_CHIP_COFFEELAKE_U_GT2_2  0x3EA3
+#define PCI_CHIP_COFFEELAKE_U_GT2_3  0x3EA9
+
+#define PCI_CHIP_COFFEELAKE_U_GT3_1  0x3EA2
+#define PCI_CHIP_COFFEELAKE_U_GT3_2  0x3EA5
+#define PCI_CHIP_COFFEELAKE_U_GT3_3  0x3EA6
+#define PCI_CHIP_COFFEELAKE_U_GT3_4  0x3EA7
+#define PCI_CHIP_COFFEELAKE_U_GT3_5  0x3EA8
+
+#define IS_CFL_GT1(devid) \
+(devid == PCI_CHIP_COFFEELAKE_S_GT1_1 || \
+ devid == PCI_CHIP_COFFEELAKE_S_GT1_2 || \
+ devid == PCI_CHIP_COFFEELAKE_S_GT1_3 || \
+ devid == PCI_CHIP_COFFEELAKE_U_GT1_1 || \
+ devid == PCI_CHIP_COFFEELAKE_U_GT1_2)
+
+#define IS_CFL_GT2(devid) \
+(devid == PCI_CHIP_COFFEELAKE_S_GT2_1 || \
+ devid == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
+ devid == PCI_CHIP_COFFEELAKE_S_GT2_3 || \
+ devid == PCI_CHIP_COFFEELAKE_S_GT2_4 || \
+ devid == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
+ devid == PCI_CHIP_COFFEELAKE_H_GT2_2 || \
+ devid == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
+ devid == PCI_CHIP_COFFEELAKE_U_GT2_2 || \
+ devid == PCI_CHIP_COFFEELAKE_U_GT2_3)
+
+#define IS_CFL_GT3(devid) \
+(devid == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
+ devid == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
+ devid == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
+ devid == PCI_CHIP_COFFEELAKE_U_GT3_4 || \
+ devid == PCI_CHIP_COFFEELAKE_U_GT3_5)
+
+#define IS_COFFEELAKE(devid) (IS_CFL_GT1(devid) || IS_CFL_GT2(devid) || 
IS_CFL_GT3(devid))
+
+#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid) || 
IS_KABYLAKE(devid) || IS_GEMINILAKE(devid) || IS_COFFEELAKE(devid))
 
 #define MAX_OCLVERSION(devid) (IS_GEN9(devid) ? 200 : 120)
 
diff --git a/src/cl_device_id.c b/src/cl_device_id.c
index a4134404..c20f9eda 100644
--- a/src/cl_device_id.c
+++ b/src/cl_device_id.c
@@ -274,6 +274,36 @@ static struct _cl_device_id intel_glk12eu_device = {
 #include "cl_gen9_device.h"
 };
 
+static struct _cl_device_id intel_cfl_gt1_device = {
+  .max_compute_unit = 12,
+  .max_thread_per_unit = 7,

[Beignet] [PATCH 2/3] Fix enabling of fp64 extension

2018-01-31 Thread Mark Thompson

This should only be enabled after setting the default extensions, because
the default setup overwrites the current extension string rather than
adding to it.

Signed-off-by: Mark Thompson <s...@jkqxz.net>
---
 src/cl_device_id.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/cl_device_id.c b/src/cl_device_id.c
index 5e284193..a4134404 100644
--- a/src/cl_device_id.c
+++ b/src/cl_device_id.c
@@ -571,10 +571,10 @@ skl_gt1_break:
   intel_skl_gt1_device.device_id = device_id;
   intel_skl_gt1_device.platform = cl_get_platform_default();
   ret = _skl_gt1_device;
+  cl_intel_platform_get_default_extension(ret);
 #ifdef ENABLE_FP64
   cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
 #endif
-  cl_intel_platform_get_default_extension(ret);
   cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
   cl_intel_platform_enable_extension(ret, 
cl_intel_device_side_avc_motion_estimation_ext_id);
   break;
@@ -597,10 +597,10 @@ skl_gt2_break:
   intel_skl_gt2_device.device_id = device_id;
   intel_skl_gt2_device.platform = cl_get_platform_default();
   ret = _skl_gt2_device;
+  cl_intel_platform_get_default_extension(ret);
 #ifdef ENABLE_FP64
   cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
 #endif
-  cl_intel_platform_get_default_extension(ret);
   cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
   cl_intel_platform_enable_extension(ret, 
cl_intel_device_side_avc_motion_estimation_ext_id);
   break;
@@ -641,10 +641,10 @@ skl_gt4_break:
   intel_skl_gt4_device.device_id = device_id;
   intel_skl_gt4_device.platform = cl_get_platform_default();
   ret = _skl_gt4_device;
+  cl_intel_platform_get_default_extension(ret);
 #ifdef ENABLE_FP64
   cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
 #endif
-  cl_intel_platform_get_default_extension(ret);
   cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
   cl_intel_platform_enable_extension(ret, 
cl_intel_device_side_avc_motion_estimation_ext_id);
   break;
@@ -687,10 +687,10 @@ kbl_gt1_break:
   intel_kbl_gt1_device.device_id = device_id;
   intel_kbl_gt1_device.platform = cl_get_platform_default();
   ret = _kbl_gt1_device;
+  cl_intel_platform_get_default_extension(ret);
 #ifdef ENABLE_FP64
   cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
 #endif
-  cl_intel_platform_get_default_extension(ret);
   cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
   break;
 
@@ -706,10 +706,10 @@ kbl_gt15_break:
   intel_kbl_gt15_device.device_id = device_id;
   intel_kbl_gt15_device.platform = cl_get_platform_default();
   ret = _kbl_gt15_device;
+  cl_intel_platform_get_default_extension(ret);
 #ifdef ENABLE_FP64
   cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
 #endif
-  cl_intel_platform_get_default_extension(ret);
   cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
   break;
 
@@ -730,10 +730,10 @@ kbl_gt2_break:
   intel_kbl_gt2_device.device_id = device_id;
   intel_kbl_gt2_device.platform = cl_get_platform_default();
   ret = _kbl_gt2_device;
+  cl_intel_platform_get_default_extension(ret);
 #ifdef ENABLE_FP64
   cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
 #endif
-  cl_intel_platform_get_default_extension(ret);
   cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
   break;
 
@@ -745,10 +745,10 @@ kbl_gt3_break:
   intel_kbl_gt3_device.device_id = device_id;
   intel_kbl_gt3_device.platform = cl_get_platform_default();
   ret = _kbl_gt3_device;
+  cl_intel_platform_get_default_extension(ret);
 #ifdef ENABLE_FP64
   cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
 #endif
-  cl_intel_platform_get_default_extension(ret);
   cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
   break;
 
@@ -758,10 +758,10 @@ kbl_gt4_break:
   intel_kbl_gt4_device.device_id = device_id;
   intel_kbl_gt4_device.platform = cl_get_platform_default();
   ret = _kbl_gt4_device;
+  cl_intel_platform_get_default_extension(ret);
 #ifdef ENABLE_FP64
   cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
 #endif
-  cl_intel_platform_get_default_extension(ret);
   cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
   break;
 
-- 
2.11.0
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[Beignet] [PATCH 1/3] Ensure that DRM device uses the i915 driver

2018-01-31 Thread Mark Thompson

This avoids calling random ioctl()s and returning nonsensical errors for
unsupported devices.  In particular, loading is much cleaner on setups
where the driver needs to iterate over multiple devices to find the correct
one because the Intel graphics device is not the first DRM device.

Signed-off-by: Mark Thompson <s...@jkqxz.net>
---
 src/intel/intel_driver.c | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/src/intel/intel_driver.c b/src/intel/intel_driver.c
index 45719785..10fe3cc8 100644
--- a/src/intel/intel_driver.c
+++ b/src/intel/intel_driver.c
@@ -312,6 +312,26 @@ return ret;
 }
 #endif
 
+static int
+intel_driver_check_device(int dev_fd)
+{
+  // Ensure that this is actually an i915 DRM device.
+  drmVersion *version;
+  int ret;
+  version = drmGetVersion(dev_fd);
+  if (!version) {
+fprintf(stderr, "drmGetVersion(%d) failed: %s\n", dev_fd, strerror(errno));
+close(dev_fd);
+return 0;
+  }
+  ret = !strcmp(version->name, "i915");
+  drmFreeVersion(version);
+  // Don't print an error here if this device is using a different driver,
+  // because we might be iterating over multiple devices looking for a
+  // compatible one.
+  return ret;
+}
+
 LOCAL int
 intel_driver_init_master(intel_driver_t *driver, const char* dev_name)
 {
@@ -326,6 +346,11 @@ if (dev_fd == -1) {
   return 0;
 }
 
+if (!intel_driver_check_device(dev_fd)) {
+  close(dev_fd);
+  return 0;
+}
+
 // Check that we're authenticated
 memset(, 0, sizeof(drm_client_t));
 ret = ioctl(dev_fd, DRM_IOCTL_GET_CLIENT, );
@@ -356,6 +381,11 @@ dev_fd = open(dev_name, O_RDWR);
 if (dev_fd == -1)
   return 0;
 
+if (!intel_driver_check_device(dev_fd)) {
+  close(dev_fd);
+  return 0;
+}
+
 ret = intel_driver_init(driver, dev_fd);
 driver->need_close = 1;
 
-- 
2.11.0
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Re: [Beignet] Atom 3845

2018-01-27 Thread Mark Thompson

On 27/01/18 11:01, Rebecca N. Palmer wrote:
> That wording implies this is Debian beignet (upstream beignet uses the 
> wording "cl_get_gt_device(): error, unknown device: %x"), which is 1.3.0 in 
> stretch.  This should support Bay Trail, but I don't have the hardware to 
> actually try this.
> 
> Please post the output of
> 
> xrandr --listproviders
> glxinfo | grep " vendor\| renderer"
> lspci -nn | grep -e "\[03..\]:"
> 
> Supported Bay Trail devices have ID [8086:0f31] in the last of these.

Just the one device there does seem incomplete.

The kernel driver has six possible IDs including that one:

While the VAAPI driver has five:

If the device isn't present, it may well work just by adding the PCI-ID to the 
places in cl_device_data.h and cl_device_id.c matching the existing Bay Trail 
ID.  (Though of course there might be some reason these IDs are omitted that 
I'm not aware of.)

- Mark
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[Beignet] [PATCH 2/2] Enable Coffee Lake support

2018-01-23 Thread Mark Thompson

We don't need to do much here because the graphics core is the same as
Kaby Lake.
---
Tested on an 8700.  All behaviour is identical to Kaby Lake, so we can reuse 
most things after adding the PCI ID and device structure.

There will be more PCI IDs, but I've only added the one I know the meaning of 
and can test.


 backend/src/backend/gen_program.cpp |  5 +
 src/cl_device_data.h|  9 -
 src/cl_device_id.c  | 29 +++--
 3 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/backend/src/backend/gen_program.cpp 
b/backend/src/backend/gen_program.cpp
index e06ed40c..274c99c7 100644
--- a/backend/src/backend/gen_program.cpp
+++ b/backend/src/backend/gen_program.cpp
@@ -209,6 +209,8 @@ namespace gbe {
   ctx = GBE_NEW(BxtContext, unit, name, deviceID, relaxMath);
 } else if (IS_KABYLAKE(deviceID)) {
   ctx = GBE_NEW(KblContext, unit, name, deviceID, relaxMath);
+} else if (IS_COFFEELAKE(deviceID)) {
+  ctx = GBE_NEW(KblContext, unit, name, deviceID, relaxMath);
 } else if (IS_GEMINILAKE(deviceID)) {
   ctx = GBE_NEW(GlkContext, unit, name, deviceID, relaxMath);
 }
@@ -328,6 +330,7 @@ namespace gbe {
   (IS_SKYLAKE(deviceID) && 
MATCH_SKL_HEADER(binary)) || \
   (IS_BROXTON(deviceID) && 
MATCH_BXT_HEADER(binary)) || \
   (IS_KABYLAKE(deviceID) && 
MATCH_KBL_HEADER(binary)) || \
+  (IS_COFFEELAKE(deviceID) && 
MATCH_KBL_HEADER(binary)) || \
   (IS_GEMINILAKE(deviceID) && 
MATCH_GLK_HEADER(binary)) \
   )
 
@@ -436,6 +439,8 @@ namespace gbe {
 FILL_BXT_HEADER(*binary);
   }else if(IS_KABYLAKE(prog->deviceID)){
 FILL_KBL_HEADER(*binary);
+  }else if(IS_COFFEELAKE(prog->deviceID)){
+FILL_KBL_HEADER(*binary);
   }else if(IS_GEMINILAKE(prog->deviceID)){
 FILL_GLK_HEADER(*binary);
   }else {
diff --git a/src/cl_device_data.h b/src/cl_device_data.h
index 123b6192..db5272da 100644
--- a/src/cl_device_data.h
+++ b/src/cl_device_data.h
@@ -372,7 +372,14 @@
   (devid == PCI_CHIP_GLK_3x6 ||   \
devid == PCI_CHIP_GLK_2x6)
 
-#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid) || 
IS_KABYLAKE(devid) || IS_GEMINILAKE(devid))
+#define PCI_CHIP_COFFEELAKE_S_GT2   0x3E92
+
+#define IS_CFL_GT2(devid)  \
+  (devid == PCI_CHIP_COFFEELAKE_S_GT2)
+
+#define IS_COFFEELAKE(devid) (IS_CFL_GT2(devid))
+
+#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid) || 
IS_KABYLAKE(devid) || IS_GEMINILAKE(devid) || IS_COFFEELAKE(devid))
 
 #define MAX_OCLVERSION(devid) (IS_GEN9(devid) ? 200 : 120)
 
diff --git a/src/cl_device_id.c b/src/cl_device_id.c
index 5e284193..d3180258 100644
--- a/src/cl_device_id.c
+++ b/src/cl_device_id.c
@@ -274,6 +274,16 @@ static struct _cl_device_id intel_glk12eu_device = {
 #include "cl_gen9_device.h"
 };
 
+static struct _cl_device_id intel_cfl_gt2_device = {
+  .max_compute_unit = 24,
+  .max_thread_per_unit = 7,
+  .sub_slice_count = 3,
+  .max_work_item_sizes = {512, 512, 512},
+  .max_work_group_size = 256,
+  .max_clock_frequency = 1000,
+#include "cl_gen9_device.h"
+};
+
 LOCAL cl_device_id
 cl_get_gt_device(cl_device_type device_type)
 {
@@ -785,6 +795,19 @@ glk12eu_break:
   cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
   break;
 
+case PCI_CHIP_COFFEELAKE_S_GT2:
+  DECL_INFO_STRING(cfl_gt2_break, intel_cfl_gt2_device, name, "Intel(R) 
UHD Graphics Coffee Lake Desktop GT2");
+cfl_gt2_break:
+  intel_cfl_gt2_device.device_id = device_id;
+  intel_cfl_gt2_device.platform = cl_get_platform_default();
+  ret = _cfl_gt2_device;
+#ifdef ENABLE_FP64
+  cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id);
+#endif
+  cl_intel_platform_get_default_extension(ret);
+  cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id);
+  break;
+
 case PCI_CHIP_SANDYBRIDGE_BRIDGE:
 case PCI_CHIP_SANDYBRIDGE_GT1:
 case PCI_CHIP_SANDYBRIDGE_GT2:
@@ -992,7 +1015,8 @@ LOCAL cl_bool is_gen_device(cl_device_id device) {
  device == _kbl_gt3_device ||
  device == _kbl_gt4_device ||
  device == _glk18eu_device ||
- device == _glk12eu_device;
+ device == _glk12eu_device ||
+ device == _cfl_gt2_device;
 }
 
 LOCAL cl_int
@@ -1420,7 +1444,8 @@ cl_device_get_version(cl_device_id device, cl_int *ver)
 || device == _bxt18eu_device || device == _bxt12eu_device 
|| device == _kbl_gt1_device
 || device == _kbl_gt2_device || device == _kbl_gt3_device
 || device == _kbl_gt4_device || device == _kbl_gt15_device
-|| device == _glk18eu_device || device == _glk12eu_device) 
{
+|| device == _glk18eu_device || device == _glk12eu_device
+|| device == _cfl_gt2_device)

[Beignet] [PATCH 1/2] Ensure that DRM device uses the i915 driver

2018-01-23 Thread Mark Thompson

This avoids calling random ioctl()s and returning nonsensical errors for
unsupported devices.  In particular, loading is much cleaner on setups
where the driver needs to iterate over multiple devices to find the correct
one because the Intel graphics device is not the first DRM device.
---
Fixes this sort of spam from every OpenCL-using application:

$ clinfo 
DRM_IOCTL_I915_GEM_APERTURE failed: Invalid argument
Assuming 131072kB available aperture size.
May lead to reduced performance or incorrect rendering.
get chip id failed: -1 [2]
param: 4, val: 0
Number of platforms   1
  Platform Name   Intel Gen OCL Driver
  Platform Vendor Intel
  Platform VersionOpenCL 2.0 beignet 1.4 
(git-d1b99a1d)
  Platform ProfileFULL_PROFILE
  Platform Extensions 
cl_khr_global_int32_base_atomics cl_khr_global_int32_extended_atomics 
cl_khr_local_int32_base_atomics cl_khr_local_int32_extended_atomics 
cl_khr_byte_addressable_store cl_khr_3d_image_writes cl_khr_image2d_from_buffer 
cl_khr_depth_images cl_khr_spir cl_khr_icd cl_intel_accelerator 
cl_intel_subgroups cl_intel_subgroups_short cl_intel_media_block_io 
cl_intel_planar_yuv cl_khr_gl_sharing
  Platform Extensions function suffix Intel
DRM_IOCTL_I915_GEM_APERTURE failed: Invalid argument
Assuming 131072kB available aperture size.
May lead to reduced performance or incorrect rendering.
get chip id failed: -1 [2]
param: 4, val: 0
DRM_IOCTL_I915_GEM_APERTURE failed: Invalid argument
Assuming 131072kB available aperture size.
May lead to reduced performance or incorrect rendering.
get chip id failed: -1 [2]
param: 4, val: 0
DRM_IOCTL_I915_GEM_APERTURE failed: Invalid argument
Assuming 131072kB available aperture size.
May lead to reduced performance or incorrect rendering.
get chip id failed: -1 [2]
param: 4, val: 0
DRM_IOCTL_I915_GEM_APERTURE failed: Invalid argument
Assuming 131072kB available aperture size.
May lead to reduced performance or incorrect rendering.
get chip id failed: -1 [2]
param: 4, val: 0
DRM_IOCTL_I915_GEM_APERTURE failed: Invalid argument
Assuming 131072kB available aperture size.
May lead to reduced performance or incorrect rendering.
get chip id failed: -1 [2]
param: 4, val: 0

  Platform Name   Intel Gen OCL Driver
Number of devices 1
DRM_IOCTL_I915_GEM_APERTURE failed: Invalid argument
Assuming 131072kB available aperture size.
May lead to reduced performance or incorrect rendering.
get chip id failed: -1 [2]
param: 4, val: 0
DRM_IOCTL_I915_GEM_APERTURE failed: Invalid argument
Assuming 131072kB available aperture size.
May lead to reduced performance or incorrect rendering.
get chip id failed: -1 [2]
param: 4, val: 0
...


 src/intel/intel_driver.c | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/src/intel/intel_driver.c b/src/intel/intel_driver.c
index 45719785..10fe3cc8 100644
--- a/src/intel/intel_driver.c
+++ b/src/intel/intel_driver.c
@@ -312,6 +312,26 @@ return ret;
 }
 #endif
 
+static int
+intel_driver_check_device(int dev_fd)
+{
+  // Ensure that this is actually an i915 DRM device.
+  drmVersion *version;
+  int ret;
+  version = drmGetVersion(dev_fd);
+  if (!version) {
+fprintf(stderr, "drmGetVersion(%d) failed: %s\n", dev_fd, strerror(errno));
+close(dev_fd);
+return 0;
+  }
+  ret = !strcmp(version->name, "i915");
+  drmFreeVersion(version);
+  // Don't print an error here if this device is using a different driver,
+  // because we might be iterating over multiple devices looking for a
+  // compatible one.
+  return ret;
+}
+
 LOCAL int
 intel_driver_init_master(intel_driver_t *driver, const char* dev_name)
 {
@@ -326,6 +346,11 @@ if (dev_fd == -1) {
   return 0;
 }
 
+if (!intel_driver_check_device(dev_fd)) {
+  close(dev_fd);
+  return 0;
+}
+
 // Check that we're authenticated
 memset(, 0, sizeof(drm_client_t));
 ret = ioctl(dev_fd, DRM_IOCTL_GET_CLIENT, );
@@ -356,6 +381,11 @@ dev_fd = open(dev_name, O_RDWR);
 if (dev_fd == -1)
   return 0;
 
+if (!intel_driver_check_device(dev_fd)) {
+  close(dev_fd);
+  return 0;
+}
+
 ret = intel_driver_init(driver, dev_fd);
 driver->need_close = 1;
 
-- 
2.11.0
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[Beignet] [PATCH] Enable support for two-component 16-bit planes

2017-02-11 Thread Mark Thompson

This is needed to support the chroma plane of P010 surfaces being
mapped from VAAPI.

Signed-off-by: Mark Thompson <s...@jkqxz.net>
---
On 01/01/17 13:46, Mark Thompson wrote:
> ...

Ping.


 src/cl_image.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/cl_image.c b/src/cl_image.c
index d0593044..5ff459a0 100644
--- a/src/cl_image.c
+++ b/src/cl_image.c
@@ -144,7 +144,9 @@ cl_image_get_intel_format(const cl_image_format *fmt)
 case CL_RG:
   switch (type) {
 case CL_UNORM_INT8: return I965_SURFACEFORMAT_R8G8_UNORM;
+case CL_UNORM_INT16:return I965_SURFACEFORMAT_R16G16_UNORM;
 case CL_UNSIGNED_INT8:  return I965_SURFACEFORMAT_R8G8_UINT;
+case CL_UNSIGNED_INT16: return I965_SURFACEFORMAT_R16G16_UINT;
 default: return INTEL_UNSUPPORTED_FORMAT;
   };
 #if 0
-- 
2.11.0

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[Beignet] [PATCH] Apply image offset to read/write/map operations

2016-08-31 Thread Mark Thompson

If an image is created from a buffer, it need not start at the
beginning of the containing mappable object (especially for an image
with multiple planes, such as one created from VAAPI).  This fixes
the implementation of the clEnqueue{Read,Write,Map}Image functions to
take that offset into account.

Signed-off-by: Mark Thompson <s...@jkqxz.net>
---
v2: Added a more descriptive commit message and s-o-b line.

Thanks,

- Mark

 src/cl_enqueue.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/cl_enqueue.c b/src/cl_enqueue.c
index 081ffce..54c0ffa 100644
--- a/src/cl_enqueue.c
+++ b/src/cl_enqueue.c
@@ -204,7 +204,7 @@ cl_int cl_enqueue_read_image(enqueue_data *data)
 goto error;
   }

-  size_t offset = image->bpp*origin[0] + image->row_pitch*origin[1] + 
image->slice_pitch*origin[2];
+  size_t offset = image->offset + image->bpp*origin[0] + 
image->row_pitch*origin[1] + image->slice_pitch*origin[2];
   src_ptr = (char*)src_ptr + offset;

   if (!origin[0] && region[0] == image->w && data->row_pitch == 
image->row_pitch &&
@@ -246,8 +246,8 @@ cl_int cl_enqueue_write_image(enqueue_data *data)
 err = CL_MAP_FAILURE;
 goto error;
   }
-  //dst need to add offset
-  cl_mem_copy_image_region(data->origin, data->region, dst_ptr,
+  cl_mem_copy_image_region(data->origin, data->region,
+   dst_ptr + image->offset,
image->row_pitch, image->slice_pitch,
data->const_ptr, data->row_pitch,
data->slice_pitch, image, CL_TRUE, CL_FALSE);
@@ -311,7 +311,7 @@ cl_int cl_enqueue_map_image(enqueue_data *data)
 err = CL_MAP_FAILURE;
 goto error;
   }
-  data->ptr = ptr;
+  data->ptr = (char*)ptr + image->offset;
   if (image->image_type == CL_MEM_OBJECT_IMAGE1D_ARRAY)
 row_pitch = image->slice_pitch;
   else
-- 
2.9.3

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[Beignet] [PATCH] Apply image offset to read/write/map operations

2016-08-29 Thread Mark Thompson

---
Hi,

My use-case for this is to allow read/write/map on images created from buffers. 
 This is helpful for interoperability with VAAPI (i965) because the driver 
there wants an incoming image to be a single DRM object, even if it has 
multiple planes: making a single buffer and then creating images within that 
buffer satisfies this constraint, but without this patch planes with an offset 
from the start of the buffer do not work correctly.

I am somewhat dubious about this patch and would welcome thoughts about the 
use-case - it seems like what I have could interact badly with some other part 
of the system I'm not aware of, though it does work nicely for the specific 
case.

Tested and working on Haswell GT2 (4500U) and Skylake GT2 (6300).

Thanks,

- Mark


 src/cl_enqueue.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/cl_enqueue.c b/src/cl_enqueue.c
index 081ffce..54c0ffa 100644
--- a/src/cl_enqueue.c
+++ b/src/cl_enqueue.c
@@ -204,7 +204,7 @@ cl_int cl_enqueue_read_image(enqueue_data *data)
 goto error;
   }

-  size_t offset = image->bpp*origin[0] + image->row_pitch*origin[1] + 
image->slice_pitch*origin[2];
+  size_t offset = image->offset + image->bpp*origin[0] + 
image->row_pitch*origin[1] + image->slice_pitch*origin[2];
   src_ptr = (char*)src_ptr + offset;

   if (!origin[0] && region[0] == image->w && data->row_pitch == 
image->row_pitch &&
@@ -246,8 +246,8 @@ cl_int cl_enqueue_write_image(enqueue_data *data)
 err = CL_MAP_FAILURE;
 goto error;
   }
-  //dst need to add offset
-  cl_mem_copy_image_region(data->origin, data->region, dst_ptr,
+  cl_mem_copy_image_region(data->origin, data->region,
+   dst_ptr + image->offset,
image->row_pitch, image->slice_pitch,
data->const_ptr, data->row_pitch,
data->slice_pitch, image, CL_TRUE, CL_FALSE);
@@ -311,7 +311,7 @@ cl_int cl_enqueue_map_image(enqueue_data *data)
 err = CL_MAP_FAILURE;
 goto error;
   }
-  data->ptr = ptr;
+  data->ptr = (char*)ptr + image->offset;
   if (image->image_type == CL_MEM_OBJECT_IMAGE1D_ARRAY)
 row_pitch = image->slice_pitch;
   else
-- 
2.9.3

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[Beignet] [PATCH 3/3] Enable Coffee Lake support

[Beignet] [PATCH 2/3] Fix enabling of fp64 extension

[Beignet] [PATCH 1/3] Ensure that DRM device uses the i915 driver

Re: [Beignet] Atom 3845

[Beignet] [PATCH 2/2] Enable Coffee Lake support

[Beignet] [PATCH 1/2] Ensure that DRM device uses the i915 driver

[Beignet] [PATCH] Enable support for two-component 16-bit planes

[Beignet] [PATCH] Apply image offset to read/write/map operations

[Beignet] [PATCH] Apply image offset to read/write/map operations

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