On 2018-11-28 11:55 a.m., Dave Taht wrote:
> Thank you for that. I do have a long standing dream of a single chip
> wifi router, with the lowest SNR possible, and the minimum number of
> pins coming off of it. I'd settle for 32MB of (static?) ram on chip as
> that has proven sufficient to date to
On Wed, Nov 28, 2018 at 8:55 AM Dave Taht wrote:
>
> Bruno George Moraes writes:
>
> > Nice resource, thanks.
> >
> > If someone wonders why things look the way they do, so it's all about
> > on-die and off-die memory. Either you use off-die or on-die memory, often
> > SRAM which requires 6
That would be really cool: I loved the Mips we had at YorkU.ca
--dave
On 2018-11-28 2:02 p.m., Dave Taht wrote:
I really don't know a whole heck of a lot about where mips is going.
Certainly they remain strong in the embedded market (I do like the
edgerouter X a lot), but as for their current
I really don't know a whole heck of a lot about where mips is going.
Certainly they remain strong in the embedded market (I do like the
edgerouter X a lot), but as for their current direction or future
product lines, not a clue.
I used to know someone over there, maybe he's restored new
On 2018-11-28 11:55 a.m., Dave Taht wrote:
Thank you for that. I do have a long standing dream of a single chip
wifi router, with the lowest SNR possible, and the minimum number of
pins coming off of it. I'd settle for 32MB of (static?) ram on chip as
that has proven sufficient to date to drive
Bruno George Moraes writes:
> Nice resource, thanks.
>
> If someone wonders why things look the way they do, so it's all about
> on-die and off-die memory. Either you use off-die or on-die memory, often
> SRAM which requires 6 gates per bit. So spending half a billion gates
> gives you
>
> Nice resource, thanks.
>
> If someone wonders why things look the way they do, so it's all about
> on-die and off-die memory. Either you use off-die or on-die memory, often
> SRAM which requires 6 gates per bit. So spending half a billion gates
> gives you ~10MB buffer on-die. If you're doing
On Sat, 24 Nov 2018, Dave Taht wrote:
https://people.ucsc.edu/~warner/buffer.html
Nice resource, thanks.
If someone wonders why things look the way they do, so it's all about
on-die and off-die memory. Either you use off-die or on-die memory, often
SRAM which requires 6 gates per bit. So
https://people.ucsc.edu/~warner/buffer.html
--
Dave Täht
CTO, TekLibre, LLC
http://www.teklibre.com
Tel: 1-831-205-9740
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