Re: [PATCH v2 2/2] Add RISC-V support content to the EBBR specification

2020-10-19 Thread Atish Patra
On Mon, 2020-10-19 at 11:50 +0100, Daniel Thompson wrote: > On Fri, Oct 16, 2020 at 12:33:07PM -0700, Atish Patra wrote: > > On Fri, Oct 16, 2020 at 4:29 AM Daniel Thompson > > wrote: > > > On Thu, Oct 15, 2020 at 06:10:32PM -0700, Atish Patra wrote: > > > > + M Mode > > > > + Machine mode

Re: [PATCH v2 2/2] Add RISC-V support content to the EBBR specification

2020-10-19 Thread Daniel Thompson
On Fri, Oct 16, 2020 at 12:33:07PM -0700, Atish Patra wrote: > On Fri, Oct 16, 2020 at 4:29 AM Daniel Thompson > wrote: > > On Thu, Oct 15, 2020 at 06:10:32PM -0700, Atish Patra wrote: > > > + M Mode > > > + Machine mode is the most secure and privileged mode in RISC-V. > > > + > > > + S