This patch adds all the required content to make RISC-V EBBR compatible.
The additional content is not a lot given that we just need to update the
architecture specific sections for RISC-V. Rest of the document is ISA agnostic
anyways.
Signed-off-by: Atish Patra
---
source/chapter1-about.rst
Hi Alexandre,
On Friday 07 May 2021 at 17:15:20 (+0200), Alexandre TORGUE wrote:
> Did you get time to continue some tests on this issue ?
I did try a few things, but still fail to reproduced :/
> On my side this DT is not working:
>
> memory@c000 {
> reg = <0xc000 0x2000>;
For the EBBR meeting today:
Attached is the test result report from running a recent version of
U-Boot on an iMX8 platform and parsed with the SCT_Parser tool.
g.
Forwarded Message
Subject:Re: EBBR Testing topic for today?
Date: Mon, 10 May 2021 14:22:56 +0100
Fro
Hi everyone,
Here is the agenda for today's EBBR meeting. I've tentatively got on the
schedule a discussion of UEFI compliance testing status, but I hadn't
confirmed the topic with Vincent and Heinrich ahead of time, so we might
not be ready to discuss that and it will be a short meeting today. T
