This makefile demonstrates a bug in the expansion of .VARIABLES:
$ cat Makefile.variables
MY_one := 1
MY_two := 2
$(foreach v, $(filter MY_%, $(.VARIABLES)), $(eval undefine $v))
MY_foo := foo
MY_bar := bar
all:
@echo MY Variables = $(filter MY_%, $(.VARIABLES))
$ make -f
Hello,
when I run (serial) make, it first compiles the objects files for the
first library, then links the fist library, then it compiles the object
files for the second library, then links the second library. Finally,
for each executable, it compiles the object files and links.
When I run
I have the feeling that the second algorithm has a bottleneck:
The algorithm you describe is a feature of your makefile(s) rather than make.
Make doesn't really know about the traditional three phases of a large C
project that you describe. It's just as happy driving an assembler, preparing
