Re: FS bit on sstatus csr set on riscv64

2023-09-21 Thread Mark Kettenis
> Date: Thu, 21 Sep 2023 10:23:45 +0200 > From: "Peter J. Philipp" > > Hi, > > I don't know if it's the same on Sifive based CPU's but on the D1 > (doesn't boot beyond main() yet) the FS bits are set. These are floating > point indicators, and I thought these should be off? In my debugs I

FS bit on sstatus csr set on riscv64

2023-09-21 Thread Peter J. Philipp
Hi, I don't know if it's the same on Sifive based CPU's but on the D1 (doesn't boot beyond main() yet) the FS bits are set. These are floating point indicators, and I thought these should be off? In my debugs I have found this: 10100111 p