On Sun, Sep 17, 2023 at 04:51:11PM +0200, Peter J. Philipp wrote:
> On Sun, Sep 17, 2023 at 04:22:14PM +0200, Mark Kettenis wrote:
> > > Date: Sun, 17 Sep 2023 12:40:29 +0200
> > > From: "Peter J. Philipp"
> >
> > Sorry Peter,
> >
> > But this doesn't make any sense to me. Your C code is just
On Sun, Sep 17, 2023 at 04:22:14PM +0200, Mark Kettenis wrote:
> > Date: Sun, 17 Sep 2023 12:40:29 +0200
> > From: "Peter J. Philipp"
>
> Sorry Peter,
>
> But this doesn't make any sense to me. Your C code is just as
> unreadable as the assembly code ;)
>
> And your explanation doesn't make
On Sun, Sep 17, 2023 at 04:51:11PM +0200, Peter J. Philipp wrote:
> On Sun, Sep 17, 2023 at 04:22:14PM +0200, Mark Kettenis wrote:
> > > Date: Sun, 17 Sep 2023 12:40:29 +0200
> > > From: "Peter J. Philipp"
> >
> > Sorry Peter,
> >
> > But this doesn't make any sense to me. Your C code is just
On Sun, Sep 17, 2023 at 04:51:11PM +0200, Peter J. Philipp wrote:
> If you do find that there is some truth to my translation from asm to C,
> then the last 200 MiB is weird. Is that where the stack resides in the
> boot btw? I dunno.
Sorry this should say 2MiB, I have too many 0x20 in my
On Sun, Sep 17, 2023 at 04:22:14PM +0200, Mark Kettenis wrote:
> > Date: Sun, 17 Sep 2023 12:40:29 +0200
> > From: "Peter J. Philipp"
>
> Sorry Peter,
>
> But this doesn't make any sense to me. Your C code is just as
> unreadable as the assembly code ;)
Yeah it should be torn out and
> Date: Sun, 17 Sep 2023 12:40:29 +0200
> From: "Peter J. Philipp"
Sorry Peter,
But this doesn't make any sense to me. Your C code is just as
unreadable as the assembly code ;)
And your explanation doesn't make sense. The code works fine on
existing hardware supported by OpenBSD. Your
Hi OpenBSD/riscv64'ers!
After a week of debugging a different issue I noticed this issue with the
L2 cache in locore.S:
The physical address of the base boot memory is held in register s9,
and this is shifted by the L2 cache code by 21 to the right. In order to
make 2 MiB offsets. However, I
