On Tue, 19 Apr 2022 11:22:37 GMT, Thomas Stuefe wrote:
> LGTM
>
> Cheers, Thomas
>
> P.S. I assume you did not run the whole gamut of jtreg tests, right? Seems to
> me there are a number of tests which would need to get adapted for riscv32.
Thanks for the review, Thomas. Currently, we only
On Tue, 19 Apr 2022 08:47:18 GMT, Feilong Jiang wrote:
>> This patch adds Zero support for the 32-bit RISC-V architecture.
>>
>> Additional tests:
>>
>> - [x] Linux zero RISCV32 cross-compilation
>> - [x] Resulting binaries run on QEMU User mode without problems
>
> Feilong Jiang has updated
On Tue, 19 Apr 2022 08:47:18 GMT, Feilong Jiang wrote:
>> This patch adds Zero support for the 32-bit RISC-V architecture.
>>
>> Additional tests:
>>
>> - [x] Linux zero RISCV32 cross-compilation
>> - [x] Resulting binaries run on QEMU User mode without problems
>
> Feilong Jiang has updated
> This patch adds Zero support for the 32-bit RISC-V architecture.
>
> Additional tests:
>
> - [x] Linux zero RISCV32 cross-compilation
> - [x] Resulting binaries run on QEMU User mode without problems
Feilong Jiang has updated the pull request incrementally with one additional
commit since
On Mon, 18 Apr 2022 15:27:07 GMT, Yadong Wang wrote:
>> Feilong Jiang has updated the pull request incrementally with one additional
>> commit since the last revision:
>>
>> adjust SYS_futex define for RISCV32
>
> src/hotspot/os/linux/waitBarrier_linux.cpp line 44:
>
>> 42: #ifndef
