Hi Glenn,
I'm actually in the process of doing this partway for the biplex
unscramblers. For large FFTs, the arbitrary reorders consume an
insanely huge number of resources trying to get the mapping ROM.
Since the biplex unscramble reorders use a known and easily-described
reorder, I was just
Hi Henry,
I haven't put much effort into this so far, so I will wait on yours. At
first I was dubious of espresso (not the algorithm, just having to call
external programs), but it does seem to work well. Unless there are
liscensing issues, it seems like it would be easier to use espresso, since I
I would avoid hardcoding the case for biplex FFTs, if you can avoid
it. It's a much better solution to get the general reorder block to
work. The pink blocks did use espresso to do the logic reduction in
reorder blocks, and that resulted in slow simulation. Once it was
determined that ROMs used
For simpler logic, the logic reduction seems to work, but the casper_library
FFT has always been rather bloated in comparison to the astro_library ones,
and I think the unscrambler is the cause.
I don't think the synthesizer is good enough to recognize
I just threw together a quick design which has two roms, one with ''use
placement information turned on and one with it off, and also my port of
the espresso map block. I'm going to test them with various maps and see how
the implementations look. Any specific maps I should try?
Glenn
On Thu, Sep
Well that's interesting. I just ran this test with the map
bit_rev(0:1023,10) and both distributed ROMs seem to have been implemented
in their entirety, with no logic reduction. So clearly the synthesis is not
optimizing well at all, even for such a simple map. The espresso map ended
up as simply
Regarding simulation speed, it does take a while to generate a map of size
2^15, but the save state logic works well, and this only happens when the
parameters are changed. Updating the design after initially setting the
parameters does not take an appreciable amount of time. Simulating a map of
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