Re: [casper] ROACH 10GbE configuration problem

Hi Jason, Thank you very much for your information. I will try again. Thanks and Regards, Wei-Chung - Original Message - From: "Jason Manley" To: "Wei-Chung Hsieh" Cc: Sent: Tuesday, October 27, 2009 8:07 PM Subject: Re: [casper] ROACH 10GbE configuration problem Hi Wei-Chung

Re: [casper] Xilinx MAXDELAY constraint compiler bug

Hey Suraj. I've been working on Verilog code that requires the application of a MAXDELAY constraint to an 8 bit data bus output from a register explicitly forced into the Input/Output Buffer. When I apply the constraint to the whole bus, PAR results show that the Xilinx tools attempt to a

Re: [casper] guidelines

Hi Casperites I, too, am looking for a logo. Something bigger than the 75px x 75px banner on the website. It might be convenient to make a "press material" page on the wiki which includes some sample hardware images, logos, style sheets etc. I am busy creating a LaTeX style sheet now for

Re: [casper] ROACH 10GbE configuration problem

Hi Wei-Chung Yes, the shipping versions of tcpborphserver do not allow multiple versions of tgtap at the same time and are the cause of the errors you describe (as outlined on the wiki page). I recommend you install a new version from here: http://casper.berkeley.edu/svn/trunk/roach/sw/bin

[casper] ROACH 10GbE configuration problem

Dear All, I am new to ROACH platform and currently I'm trying to bring up the ROACH 10GbE interface as the new ROACH 10GbE tutorial do. http://casper.berkeley.edu/wiki/ROACH_10GbE_tutorial But the python scripts does not seem to bring up the 10GbE interfaces successfully. I also noticed that Jaso