Hi Laura,
For FPGA utilization, I look at the file:
sysgen/synth_model/modelfilename_cw.syr
Mark
On Wed, Nov 18, 2009 at 2:26 PM, Laura Spitler wrote:
> Hi everyone,
>
> I have a general question about over mapping a design. What's the
> easiest way to determine by how much I've over utilized
Hi Laura,
At least with 7.1, the output of system generator includes a log file
that gives some rough usage numbers. The IO will always be overmapped
in these reports because all of the connections for shared registers
and brams and such are considered IO pins, but you may be able to get
some usefu
Hi everyone,
I have a general question about over mapping a design. What's the
easiest way to determine by how much I've over utilized the chip?
The log files don't seem to give a resource summary when mapping fails
with an error.
Thanks!
Laura
mo ohady m...@digicom.org
On 11/18/2009 10:46 AM, Karl Warnick wrote:
Hi all,
I'd like to get in touch with Mo at Digicom to see if there are any
boards currently available. Could someone provide contact information
(or information on available boards from the most recent run)?
Thanks,
K
Stan,
Since this is my first post to the casper list, I'm going to reply with
a "thanks." I'll be less verbose in the future :).
Karl
Stan Kurtz wrote:
On Wed, 18 Nov 2009, Karl Warnick wrote:
Hi all,
I'd like to get in touch with Mo at Digicom to see if there are any
boards currently avai
On Wed, 18 Nov 2009, Karl Warnick wrote:
Hi all,
I'd like to get in touch with Mo at Digicom to see if there are any boards
currently available. Could someone provide contact information (or
information on available boards from the most recent run)?
Thanks,
Karl
Hi Karl,
I was in touch w
Hi all,
I'd like to get in touch with Mo at Digicom to see if there are any
boards currently available. Could someone provide contact information
(or information on available boards from the most recent run)?
Thanks,
Karl
--
Karl F. Warnick email: warn...@by
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