Hi Dave, Rick,
There are constraints in Verilog for this (IOB=TRUE and LOC), but I
suspect that the tools may have trouble passing the port connectivity
upstream. Since the Simulink design gets used as a sub-component of
a larger project, all of the connectivity to external and inter-module
Correct, it doesn't work. You can attach the constraints in Verilog
(eg, (* LOC = B11 *)), and it compiles in the Xilinx IDE, but the
casper tools tell me that all the ports need to be connected to GPIO
blocks, or something.
My next attempt is to simply use the gpio yellow block as a bunch of
Bummer. I used this on the ATA F board design, but it was not done
using the CASPER toolflow. Maybe a small modification to the
CASPER toolflow to change this to a warning rather than an error
would make it workable for you.
Dave
On May 11, 2010, at 7:31 , Rick Raffanti wrote:
Correct,
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