[casper] ROACH2 XAUI

Hi all, I'm considering an application for ROACH2 which would require a load of point-to-point 10Gb/s connections. Has anyone got XAUI running on ROACH2 with either of the available mezzanine cards? If not, are there likely to be any major obstacles to getting this working? Cheers, Jack

Re: [casper] ROACH2 XAUI

We've tried to use XAUI with the SFP cards and that failed. There's something weird with the PHYs, and attempts to get help from Vitesse fell on deaf ears. But it should be possible to use the CX4 interfaces. Jason On 06 Nov 2013, at 14:49 , Jack Hickish wrote: Hi all, I'm considering an

Re: [casper] ROACH2 XAUI

Hi Jack Do you need 10Ge links or XAUI? The 10Ge yellow blocks work fine on ROACH2. One of the outstanding yellow blocks for ROACH2 is the XAUI block. The 10Ge yellow blocks use a quad core XAUI core underneath which takes care of bonding the individual streams together so it will not quite

Re: [casper] ROACH2 XAUI

Hi jack My mistake. You should be able to use the quad core XAUI core underneath the existing 10Ge block. Cheers Hi Jack Do you need 10Ge links or XAUI? The 10Ge yellow blocks work fine on ROACH2. One of the outstanding yellow blocks for ROACH2 is the XAUI block. The 10Ge yellow blocks

Re: [casper] ROACH2 XAUI

Thanks, all, Food for thought... (I'm trying to weigh up the pros and cons of using a cheaper switchless correlator but having to make more custom firmware vs just using a switch and participating in mass IP theft from various CASPER github repos) Cheers, Jack On 6 November 2013 13:45, Andrew

Re: [casper] ROACH2 XAUI

Dave and the Australian Redback team might disagree with me here, but with 10GbE switch ports now costing less than $100 ea, I reckon if you need to go off-board, just use a switch. It gives you so many more options for a (usually negligible) incremental system cost. Jason On 06 Nov 2013, at

Re: [casper] adc5g block run at 2500MHz

Hi Weiwei, In most cases, as long as you run your design below the successfully-compiled-for clock rate, i.e. the clock rate at which the Xilinx tools have guaranteed timing for you, you should be okay. This is complicated by the fact that the clock goes through an MMCM which has various