Does anyone have experience using chipScope with Platform Cable USB II on
roach2? I know it is not necessary given all the CASPER superstructure, but
does anything on the roach2 prevent it?
--
David P. Saroff
Rochester Institute of Technology
54 Lomb Memorial Dr, Rochester, NY 14623
I used the technique outlined here to track the java heap memory usage:
http://www.mathworks.com/matlabcentral/answers/95990
It peaks at 190 MB then proceeds to see-saw between 40 and 190 MB, so java heap
memory is not an issue. Neither is RAM in general. This isn't a resource
constraint issue.
Running out of disk space or permissions problems with temp directories can
cause super slow compiles. We ran into something (vaugely) similar as we had
multiple people running compiles at once causing havoc in temp directories.
You might try explicitly setting these in your simulink
Hi David yes the ftdi chip hogs the bus. Ill send you a script to release
the jtag when I get into the office.
Regards
Wes
On 20 Nov 2013 21:53, DAVID SAROFF (RIT Student) dps7...@rit.edu wrote:
Does anyone have experience using chipScope with Platform Cable USB II on
roach2? I know it is not
You can run this script
https://github.com/ska-sa/roach2_support_software/blob/master/ftdi/scripts/release_jtag_port.py
You will need python and the ftdi libraries.
Wesley New
South African SKA Project
+2721 506 7365
www.ska.ac.za
On Thu, Nov 21, 2013 at 7:49 AM, Wesley New wes...@ska.ac.za
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