Hi,simon,
I'm meeting the same issue.I failed to compile the mdl which used to be
compiled successfully.
In my opinion,The timing error may be a compile EDK problem.So I want to
Disable the timing error first. I have tried some compilations,I put the XPS%
xset enable_par_timing_error 0 when the
Running casper toolflow on windows need a little modification of some .m files.
I recommend using xilinx officially supported linux distributions, RHEL 6 or
it's clone, centos 6, with casper toolflow. But if you insist running on
windows, contact me and I can give you some patch.
Good luck,
Helllo ,
I have a simple question, my system configuration is windows7, and xilinx 14.7
with matlab2012a, but the casper_xps warns that it can not work with
xilinx14.7, but i see on the casper website that
Matlab R2012a/b
Xilinx v14.x (Latest 14.7)
is ok, so i am confused , is windows not ok
HI Marc,
Thank you for the reply, I am not seeing anything on the serial
terminal. I have ordered a macraigor wiggler, I will try using that and see
if the roach starts working.
Thanks and regards,
Nishanth
On Mon, May 4, 2015 at 12:28 AM, Marc Welz m...@ska.ac.za wrote:
On Wed, Apr 29,
dear vishwa,
there are no SFP+ to RJ45 cables,
but you can purchase SFP+ to SFP+ cables,
and use these cables to connect a Roach2 to
another Roach2, or to a 10Gbit SFP+ switch,
or a 10Gbit SFP+ network interface card in a computer.
these SFP+ cables are made by several dozen vendors.
for short
Hi Casperites,
I'm trying to run tutorial 2 to understand how the 10GbE works, but don't
have a CX4 cable.
Does anyone have a spare that I could borrow for a couple weeks?
Thanks,
Brad Dober
Ph.D. Candidate
Department of Physics and Astronomy
University of Pennsylvania
Cell: 262-949-4668
White rabbit is the version of IEEE1588 that locks bit clocks. Normal IEEE1588
doesn't do this. For this reason, (last I looked), there was no 10G
implementation. 1G speeds is the highest White Rabbit implementation. The HW
support for normal IEEE1588 is used to timestamp the packets without
hi dave,
i also think distributing clock and 1 PPS is simpler than IEEE1588.
some of the IEEE1588 and white rabbit experts are here at berkeley.
see for example:
http://chess.eecs.berkeley.edu/pubs/881/dreams.pdf
my limited understanding is that 1588 phase locks the bit clocks of
routers and
Hi
We have a complete White Rabbit setup, including 5km fibre test reels. It
is driven by a Meinberg Plenum 1 clock. We are quite happy to chat with
anyone on this topic of phase coherence. As you all know, the hardware and
firmware is all Open Source, so as Jason mentions, easy to incorporate. I
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