Re: [casper] ADC 5g testing

Hi Amit, Firstly, 160 MHz clock rate for the FPGA is not too low. We've run the FPGA at 143 MHz and 156 MHz without issue (for ADC5g sample rates of 2288 MHz and 2496 MHz). Going back to the basics: - Are both ADC yellow blocks configured exactly the way? Could you send a screenshot of their

Re: [casper] ADC 5g testing

Hi Jack, Thanks for the input. Actually that's what I am doing. I am taking every 4th output to get Nyquist bw of 320MHz. Is this clock rate is too low for the FPGA? Cheers, Amit On 19 June 2016 00:35:25 CEST, Jack Hickish wrote: >Hi Amit, > >For what it's worth, you

Re: [casper] ADC 5g testing

Hi Amit, For what it's worth, you can always just run the ADC faster, but only use a subset of the yellow block outputs. Eg., clock the ADC at 1280MHz, and use every 8th yellow block output. This can be handy because 1. You get to avoid whatever edge cases exist which cause various blocks to

[casper] ADC 5g testing

Dear All, I am trying to test the ADC output for a simple sinusoid input signal (75 MHz, -6dBm) with the snapshot block. Many of the output values are not consistent with the expected results. Do I need to do any post-processing on data after reading from Bram ? Regards, Amit