Hello Suraj
Thanks for you explanation.
Maybe I don't describe clearly.
I mean if I want program the FPAG on ROACH over JTAG.
Also, the bit file is generated by Xilinx ISE not CASPER toolflow.
In this moment, the ucf file of my design is only included the IO pins of my
design.
But a lot of
If you already have a bitstream, simply plug a JTAG programmer into P2
(labelled Xilinx JTAG), and use IMPACT.
But if I read your email correctly, you haven't configured clocks or
anything so I'm not sure what the point of this exercise is. I agree
with Suraj, easiest would be to start
Hello,
On Nov 3, 2009, at 6:39 PM, C-H Cheng wrote:
Hello All
If I want to simulate a design in ISE and generate a bit file to
download to ROACH over JTAG.
You can do this using the .bit generated by the CASPER toolflow,
available in the same location as the .bof. bof files are generated
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