Dear Caspers,
Currently, I am experimenting with roach2 boards and trying to compile the
‘tut_spec’ with small modifications but have an issue with Casper DSP block
‘pfb_fir_real’. I can add it from the library to the model but cannot seem
to change the parameters. Once I ied to change any
I think this might be a mismatch between the Ethernet memory map compiled
into the firmware vs expected by casperfpga. What version of casperfpga are
you using?
Cheers
Jack
On Wed, 28 Feb 2024 at 15:25, Sivakumar Sivasankar
wrote:
> Dear Caspers,
> I am a research student at FIU,
Hi Yufan,
Sorry this did not resolve your issues. I believe I see the issue now and am
sorry I did not catch this earlier. In your previous screenshots for the
configuration of the RFDC the PLL reference clock input is set to 245.76 MHz
when it should be set to 491.52 MHz. The LMX file you are
Hi Jack,
Thanks for the reply. I am using the below version of casperfpga.
casperfpga 0.4.4.dev1336+py38.276ee44
Do I need to change the casperfpga version?
Sivasankar.S
On Wed, Feb 28, 2024 at 9:28 PM Jack Hickish wrote:
> I think this might be a mismatch between the
I'd suggest start by trying the casperfpga which is included as a git
submodule in the tutorials repo --
https://github.com/casper-astro/casperfpga/tree/a88f9af0b16e6a12fe51884d29c162e76e7c21a6
I'm guessing this is substantially older than the one you are using, and
may be python2.7 only.
As
Hi Bishnu and Mitch,
Thank you so much for your help! I am very sorry I did not look at that before
and only focused on the tutorial which have a snapshot for RFDC config that use
245.76MHz. I have now solved the question and the ADC status is 15 with PLL
working! Now I can figure out the fix
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