Hi John,
Do you have the coefficients in slices rather than BRAMs? That might
be contributing to the high address fanout.
Yes, the use distributed memory cells for coeffs is checked. I'll try
changing it. It takes forever to build, but I'll start one and leave it
go.
This made a
I think this makes a lot of sense, and now that you mention it I think
I recall having similar experiences. Distributed RAM involves making
up the coefficient memory, some few Kbytes, out of ~16x1 bit memory
elements, so the address logic has to fan out to all of those tiny
elements. The BRAM (I
Hi all:
I just could not find any documents in casper web site talking about the
control software running in the PowerPC.
So my first question is how can I use the interface between FPGA and
PowerPC? For example, how can I design a block memory which can be written
by ADC module and can be
hi wan,
regarding your question on roach I/O:
in about a month, roach will be running BORPH,
a linux operating system for fpga's
(the operating system we use on the BEE2).
in BORPH, registers, block rams and fifo's
in your simulink design appear as linux files
which you can read and write.
4 matches
Mail list logo
