A note to all those who are interested in or are using the 10Ge V2 core,
it now supports frame sizes of 8704 bytes, and will resolve the issues
discussed earlier in this thread. These changes apply from CASPER SVN
revision 2019.
Cheers,
David
Hi All.
On 10GbEv2 it is 8192, plus UDP and IP headers etc. But there would be
no space for your application headers.
This is correct, 8k is the V2 limit. There are a few problems with the
current implementation, firstly it would be far more useful to support
8k data payload + some
Hi. Does anybody know the actual limit on packet size for the
original xilinx and the V2 10 GbE cores? The documents say something
vague like about 8k bytes, but is there a known hard limit to the packet
size in each case?
We want to package up 8K (8192) bytes of data + a few words of framing,
On 10GbEv2 it is 8192, plus UDP and IP headers etc. But there would be
no space for your application headers.
When we specc'd it originally, the thought here was that 8192b is the
closest power-of-2 for BRAM sizing to that same 9216b limit for most
NICs. If we wanted to get to 9000, we'd
On 10GbEv2 it is 8192, plus UDP and IP headers etc. But there would be
no space for your application headers.
When we specc'd it originally, the thought here was that 8192b is the
closest power-of-2 for BRAM sizing to that same 9216b limit for most
NICs. If we wanted to get to 9000, we'd
5 matches
Mail list logo
