On 2016-08-24 3:24 PM, Don North wrote:
On 8/24/2016 2:21 AM, Pontus Pihlgren wrote:
On Tue, Aug 23, 2016 at 12:31:42PM -0700, Scott Baker wrote:
Hi,
1) DEC documentation which more fully describes all the instruction
set (in
more detail than the PDP-8 handbook)
Not DEC documentation but a
On 8/24/2016 2:21 AM, Pontus Pihlgren wrote:
On Tue, Aug 23, 2016 at 12:31:42PM -0700, Scott Baker wrote:
Hi,
1) DEC documentation which more fully describes all the instruction set (in
more detail than the PDP-8 handbook)
Not DEC documentation but a good resource:
Kudos for working on a VHDL model. Which 8 variant are you trying to model?
As others have stated, the IAC does affect the link. Of the other
instructions that one might think could change the Link, the ISZ
instruction does not affect the link and indirection that uses the
autoincrement memory
WHICH PDP-8?
Every implementation was slightly different.
Dig up the stuff written by Charles Lasner for the gory details.
On 8/23/16 12:31 PM, Scott Baker wrote:
> Hi,
>
> I have written a PDP-8 VHDL model and I have it running in an FPGA
> https://github.com/scottlbaker/PDP8-SOC
>
>
On 8/23/2016 12:31 PM, Scott Baker wrote:
Hi,
I have written a PDP-8 VHDL model and I have it running in an FPGA
https://github.com/scottlbaker/PDP8-SOC
At this time it has passed a basic DEC diagnostic instruction test but
I found some interesting things when getting that instruction test to
Hi,
I have written a PDP-8 VHDL model and I have it running in an FPGA
https://github.com/scottlbaker/PDP8-SOC
At this time it has passed a basic DEC diagnostic instruction test but
I found some interesting things when getting that instruction test to pass.
For example:
The following segment of
