Re: radar history

[Adrian Stoness via cctalk]

^^ thats because they create lure around things to install fear in the
enemy remember propiganda


On Sat, Mar 3, 2018 at 12:46 AM, Chuck Guzis via cctalk <
cctalk@classiccmp.org> wrote:

> I dunno about these historical accounts.
>
> I was watching a PBS program about RADAR and the magnetron was made out
> to be a super-secret device, yet there's a clear explanation of it in my
> 1942 "Radio Handbook".
>
> --Chuck
>

Re: radar history

[Chuck Guzis via cctalk]

I dunno about these historical accounts.

I was watching a PBS program about RADAR and the magnetron was made out
to be a super-secret device, yet there's a clear explanation of it in my
1942 "Radio Handbook".

--Chuck

Re: radar history

[Ed Sharpe via cctalk]

dunno what that thing is..
Mentioned link as many of us,are,interested in a,cross section on electronivs 
history..  pike Cory, and others ..

Sent from AOL Mobile Mail

On Friday, March 2, 2018 Ian Finder  wrote:


All I have to say in response to this message is...

http://i0.kym-cdn.com/entries/icons/original/000/022/978/yNlQWRM.jpg

Re: radar history

[Ian Finder via cctalk]

All I have to say in response to this message is...
http://i0.kym-cdn.com/entries/icons/original/000/022/978/yNlQWRM.jpg

radar history

[Ed Sharpe via cctalk]

https://www.bing.com/videos/search?q=castles+in+the+sky+radar=EMMX03=%2biT2nJ5t%2bsBZvoaW.1.0.1.285=%2fsearch%3fq%3dcastles%2bin%2bthe%2bsky%2bradar%26FORM%3dEMMXAB%26PC%3dEMMX03%26refcv%3d%252BiT2nJ5t%252BsBZvoaW.1.0.1.285=detail=vwrc=16FF70654860E5B15B4E16FF70654860E5B15B4E=WRVORC

great saw,this on the 40 inch...

Sent from AOL Mobile Mail

Polymorphic 8813 Bezel

[Ben Sinclair via cctalk]

While cleaning just now I found one of the metal and black plastic side
bezels for an 8813. If anyone needs one, let me know and I can send it to
you!

-- 
Ben Sinclair
b...@bensinclair.com

IBM System/36 manuals available

[Seth Morabito via cctalk]

Folks,

I know someone in North Carolina (not on this list) who just found a small pile 
of IBM System/36 manuals in three ring binders. These are all already on 
Bitsavers, and these manuals are in pretty rough shape, but if anyone really 
really wants them, let me know and I'll pass on your contact information

5360 Vol A1 MIMS "Maintenance Information Manual - General Safety Guide (etc.)"
5360 Vol A2 MIMS "Maintenance Information Manual - CPU & Channel (etc.)"
5360 Vol A3 MIMS "Maintenance Information Manual - Work: Station (etc.)"
5360 Vol B2 MAPS "Maintenance Analysis Procedures"
5360 Vol C1 FLDS "Field Logic Diagram"

-Seth
-- 
  Seth Morabito
  w...@loomcom.com

RE: Old Classiccmp archive

[William Sudbrink via cctalk]

Livin' in a small town...
Nobody locks their door at night...

-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Jon Elson
via cctalk
Sent: Friday, March 02, 2018 11:35 AM
To: r.stricklin; gene...@ezwind.net; discuss...@ezwind.net:On-Topic and
Off-Topic Posts
Subject: Re: Old Classiccmp archive

On 03/01/2018 10:34 PM, r.stricklin via cctalk wrote:
>
> 8) Once the @ character is echoed, press enter.  You should get
>an error message (I no longer remember the text).  Now type
>"@O 77".  This instructs the TIP to connect you to the
>MIT-DM (Massachusetts Institute of Technology, Dynamic Modeling)
>computer.
>
> 9) Start pressing the return key once a second until you get a
>logon prompt (I no longer remember the prompt text).  The user
>name and password are GUEST.
>
>
Ahh, the good old days when nobody worried about security!

Jon


---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus

Re: PDP11 I/O page memory map

[Jerry Weiss via cctalk]

> On Mar 2, 2018, at 9:11 AM, Paul Koning via cctalk  
> wrote:
> 
> 
>> On Mar 2, 2018, at 8:37 AM, Noel Chiappa via cctalk  
>> wrote:
>> 
>>> From: Jerry Weiss
>> 
>>> Typically execution of the RESET instruction in a user program is
>>> treated as a NOP
>> 
>> Yeah, that's not documented in most PDP-11 CPU manuals, either. It's one of
>> the things that makes the PDP-11 impossible to virtualize; only HALT and SPL
>> trap, IIRC. M[TF]P[ID] doesn't, I think, and neither does WAIT or RT[IT],
>> IIRC.
> 
> RTI/RTT are used in the debugger, so they need to work in user mode.  They 
> refuse to raise your privilege level, though.  But an RTI in user mode that 
> returns to user mode is perfectly ok so it is valid.
> 
> The move from/to previous are also valid, by deliberate design.  This works 
> because the previous mode is explicitly encoded in the PSW, and just like the 
> current mode, cannot be raised by user mode RTI.  It is why the kernel 
> usually sets current == previous == user when constructing the PSW for a 
> process.
> 
> What does the Architecture handbook say about WAIT and RESET in non-kernel 
> modes?  I don't have mine at hand unfortunately.
> 
>   paul
> 
> 

In the Digital Microcomputer Processor Handbook 1979-80 edition page 280 
describes the user mode restrictions on HALT, RESET. and MTPS, but nothing 
about WAIT.   

The PDP11 Handbook 1979  does not  detail user mode implications for MTPS or  
WAIT.  HALT is called out for a trap to 10 in user mode.  Prevention of  a 
"restart" in user mode is mentioned on page 182, but nothing explicit about 
RESET.

As FritzM suggested, it appears there are fewer details in the PDP-11 
Architecture Handbook (1983) for these instructions than these earlier 
references above.HALT trapping to 4 appears for later processors in the 
family differences section, but I did not see much else  for this topic.

Jerry

Re: Bug-for-bug compatibility [was RE: SimH DECtape vs. Tops-10 [was RE: Writing emulators [Was: Re: VCF PNW 2018: Pictures!]]]

[allison via cctalk]

On 03/02/2018 06:44 AM, Maciej W. Rozycki via cctalk wrote:
> On Wed, 28 Feb 2018, Paul Koning via cctalk wrote:
>
>> With the VAX, this got cleaned up to a significant extent, and ditto 
>> with Alpha.  In both cases, an internal validator tool was created to 
>> verify that, at least from the point of view of instruction execution, a 
>> new machine worked the same as an existing reference machine.  But this 
>> seems to be quite an unusual notion in the history of computer hardware 
>> development generally.  Even when standard specifications exist that 
>> appear to spell out how an architecture is supposed to work, the reality 
>> is that two implementations will in general do it differently.  That is 
>> particularly likely to happen in cases of "no one will do this" -- like 
>> shifts by more than the word size, or other oddball stuff.
Its right after the VAX that DEC engineering started thinking about
standards.
It was clear that the PDP-11 was not one fully unified system as each
variant
had its own unique quirks more so after the advent of the LSI-11 and F11
chips.
Of of the PDP-11 handbooks I have has a back page of differences in
instruction
set behavior between all of the known PDP-11s including T-11 and J11,

It was clear the VAX architecture had to have a clear definition that
was true
across all of VAXen yet to come.  This was brought about by the need to
keep
VMS consistent and also later Ultrix.   Hence the DEC STD For VAX came to
being and the test for is it a VAX as well.  Exceptions were clearly
listed and
the software impacts were defined.    Of course since Alpha had to run VMS
(by then OpenVMS) and Ultrix or its heirs it also was spec'ed out fully
and for
all expected generations.

>  That's what architecture verification programs or AVP tests are for 
> nowadays.  Everything that's not undefined in the architecture is supposed 
> to work as defined.  This includes odd corner cases.  Formal definitions 
> are included in the architecture specification.
Now we do in the world.  But a good example of variations on a theme is ARM.
Though there are some controls is an earlier ARM 16bit  a subset of an ARM
64 bit?

Allison
>   Maciej

Re: PDP11 I/O page memory map

[Phil Budne via cctalk]

It might be interesting to make a virtual PDP-11 (simulator) that *IS*
more virtualization friendly, and find out how much user code depends
on the existing behavior...  And then write a PDP-11 hypervisor!

BUT existing PDP-11's aren't even friendly restarting after a page
fault, which is required for lesser virtualization (VM), and would be
necessary to simulate memory mapped devices.

I remember how each new generation of MC68K processors had ever larger
trap stack frames to hold internal processor state...

Re: PDP11 I/O page memory map

[Fritz Mueller via cctalk]

> On Mar 2, 2018, at 5:37 AM, Noel Chiappa via cctalk  
> wrote:
> 
>> From: Jerry Weiss
>> Typically execution of the RESET instruction in a user program is
>> treated as a NOP
> 
> Yeah, that's not documented in most PDP-11 CPU manuals, either. It's one of
> the things that makes the PDP-11 impossible to virtualize; only HALT and SPL
> trap, IIRC. M[TF]P[ID] doesn't, I think, and neither does WAIT or RT[IT],
> IIRC.

Re-affirming Noel's *most* from above: having been through a deep dive on the 
11/45 during a restoration the last couple years, I know most of this material 
*is* explicit in the 11/45 processor handbook, though maybe not in the obvious 
places.

Behavior of HALT, RESET, and SPL in all three modes is documented on page 13, 
in the Processor Status Word section, for example.  HALT and SPL behaviors are 
also noted on their individual instruction pages, but the RESET behavior, 
strangely, is not.

WAIT is permitted in supervisor and user modes on the 11/45.

Current and previous mode bits in the PSW can be set but not cleared when in 
supervisor and user modes on the 11/45.  RTI/RTT/M[FT]P[DI] function uniformly, 
but given this PSW behavior they can only effectively preserve or lower the 
processor mode, or access the address space of same or lower modes, assuming 
the PSW is properly setup and handled by kernel mode code.  This is documented 
on page 24 of the processor handbook, in the Multiprogramming section.

I don't recall explicit mention of the MMU reset behavior in the processor 
handbook, but it may be squirreled away in there somewhere...  I think I 
absorbed that bit of critical info from the KT11-C maintenance manual when I 
was working through debugging the one in my /45.

I am much less familiar with the documentation for later-model PDP-11s.  It 
sounds like a some of this info may have been "sanitized" from the later 
handbooks?

cheers!
  --FritzM.

Re: PDP11 I/O page memory map

[Noel Chiappa via cctalk]

> From: Paul Koning

> RTI/RTT are used in the debugger, so they need to work in user mode.
> They refuse to raise your privilege level, though.

I understand that it has uses, but by specifying the 'failure' mode in User
mode (when the contents of the current or previous modes is not User) to be
'ignore', rather than 'trap', that's one more thing that makes the PDP-11
non-virtualizable. (This choice, to ignore, instead of trap, has the same
issue in other places where it's done that way, e.g. RESET.)

 Noel

Re: Old Classiccmp archive

[Jon Elson via cctalk]

On 03/01/2018 10:34 PM, r.stricklin via cctalk wrote:


8) Once the @ character is echoed, press enter.  You should get
   an error message (I no longer remember the text).  Now type
   "@O 77".  This instructs the TIP to connect you to the
   MIT-DM (Massachusetts Institute of Technology, Dynamic Modeling)
   computer.

9) Start pressing the return key once a second until you get a
   logon prompt (I no longer remember the prompt text).  The user
   name and password are GUEST.



Ahh, the good old days when nobody worried about security!

Jon

Re: HP 1000 system in Europe

[Robert via cctalk]

Some more info would be nice.

Also, a word of caution. I have two  HP 1000/A900 systems and I gave
myself a hernia last weekend, moving them.

Robert

On Thu, Mar 1, 2018 at 7:49 AM, GerardCJAT via cctech
 wrote:
> NICE system  !!
>
> I would have love it but hadn't room for it  too sad  :-((
>
> Where did in goes ??? ( Which country, in Europ, I think ?  )
>
> Gerard

Re: PDP11 I/O page memory map

[Paul Koning via cctalk]

> On Mar 2, 2018, at 8:37 AM, Noel Chiappa via cctalk  
> wrote:
> 
>> From: Jerry Weiss
> 
>> Typically execution of the RESET instruction in a user program is
>> treated as a NOP
> 
> Yeah, that's not documented in most PDP-11 CPU manuals, either. It's one of
> the things that makes the PDP-11 impossible to virtualize; only HALT and SPL
> trap, IIRC. M[TF]P[ID] doesn't, I think, and neither does WAIT or RT[IT],
> IIRC.

RTI/RTT are used in the debugger, so they need to work in user mode.  They 
refuse to raise your privilege level, though.  But an RTI in user mode that 
returns to user mode is perfectly ok so it is valid.

The move from/to previous are also valid, by deliberate design.  This works 
because the previous mode is explicitly encoded in the PSW, and just like the 
current mode, cannot be raised by user mode RTI.  It is why the kernel usually 
sets current == previous == user when constructing the PSW for a process.

What does the Architecture handbook say about WAIT and RESET in non-kernel 
modes?  I don't have mine at hand unfortunately.

paul

Re: Is livingcomputers.org down?

[Bill Degnan via cctalk]

It's back up.

On Fri, Mar 2, 2018 at 8:34 AM, Kyle Owen via cctalk 
wrote:

> I'm not able to load Living Computer's website. Anyone else?
>
> Kyle
>

Re: PDP11 I/O page memory map

[Noel Chiappa via cctalk]

> From: Jerry Weiss

> Typically execution of the RESET instruction in a user program is
> treated as a NOP

Yeah, that's not documented in most PDP-11 CPU manuals, either. It's one of
the things that makes the PDP-11 impossible to virtualize; only HALT and SPL
trap, IIRC. M[TF]P[ID] doesn't, I think, and neither does WAIT or RT[IT],
IIRC.
  
  Noel

Is livingcomputers.org down?

[Kyle Owen via cctalk]

I'm not able to load Living Computer's website. Anyone else?

Kyle

Re: Shipping a Flexowriter

[Robert via cctalk]

+2 for Pak Mail. I used their Plainview TX franchise, last year, to
send an AS/400e, with expansion chassis, all the way from Texas to
Canada.

They came and collected it (a 250 mile round trip), built a crate for
it and sent it LTL freight. The recipient was happy.

On Thu, Mar 1, 2018 at 2:38 PM, Curious Marc via cctalk
 wrote:
> +1 on Pak Mail too.
> Marc
>
>> On Feb 27, 2018, at 12:12 PM, Chuck Guzis via cctalk  
>> wrote:
>>
>>> On 02/27/2018 11:37 AM, Ed Sharpe wrote:
>>> *In my  case  lady  worked at a  warehouse and had  her  people  palate
>>> and strap the  3 ttys!  saved $$   Pack mail is  great though  to  pack
>>> stuff if no other free reliable  option is there.   We have  to  ship a
>>>  large  group of  computer front panels  across  country  and  they
>>> handled it   really  well.
>>> *
>>>
>>> *Pack Mail  ships alot of  stuff  form many auction places too.*
>>
>> I've used *Pak Mail* several times for very large delicate items and
>> never have been disappointed.  Choose your store location, though--some
>> do not handle large things.
>>
>> One consideration is that they have contracts with the freight companies
>> and can often price shipping + packing for less than you'd get charged
>> for a single LTL shipment from a freight company.
>>
>> Have them ship it to another Pak Mail location, so you can pick it up,
>> sans pallet.
>>
>> Craters and Freighters is another good operation, though they tend to
>> operate on the East Coast.
>>
>> --Chuck
>>

Re: Bug-for-bug compatibility [was RE: SimH DECtape vs. Tops-10 [was RE: Writing emulators [Was: Re: VCF PNW 2018: Pictures!]]]

[Maciej W. Rozycki via cctalk]

On Wed, 28 Feb 2018, Paul Koning via cctalk wrote:

> With the VAX, this got cleaned up to a significant extent, and ditto 
> with Alpha.  In both cases, an internal validator tool was created to 
> verify that, at least from the point of view of instruction execution, a 
> new machine worked the same as an existing reference machine.  But this 
> seems to be quite an unusual notion in the history of computer hardware 
> development generally.  Even when standard specifications exist that 
> appear to spell out how an architecture is supposed to work, the reality 
> is that two implementations will in general do it differently.  That is 
> particularly likely to happen in cases of "no one will do this" -- like 
> shifts by more than the word size, or other oddball stuff.

 That's what architecture verification programs or AVP tests are for 
nowadays.  Everything that's not undefined in the architecture is supposed 
to work as defined.  This includes odd corner cases.  Formal definitions 
are included in the architecture specification.

  Maciej