KA650 VAX memory error

[Joseph Zatarski via cctalk]

On Sat, Mar 2, 2019 at 3:16 PM Glen Slick via cctalk
 wrote:

On Sat, Mar 2, 2019 at 12:02 PM Joseph Zatarski via cctalk
http://www.classiccmp.org/mailman/listinfo/cctalk>> 
wrote:

//>>/On a somewhat related note, I don't suppose anybody knows or has />>/documentation on the 
pinout of the C/D interconnect on these RAM boards? />>/The pinout for the ribbon cable is in the manual, 
but the C/D />>/interconnect doesn't seem to be documented in any of the manuals that />>/are 
online. />

650QS Field Maintenance Print Set, MP-02538-01, Rev C1

>http://www.bitsavers.org/pdf/dec/vax/650/MP02538_650QS_Sep88.pdf  



Page 65 of the PDF, KA650 Circuit Schematics Page 23 of 40
MA0 - MA9
CAS0 - CAS3
RAS0 - RAS3
WE
SE
XADDR20, XADDR21
+5
GND

Page 47 of the PDF, Page 5 of 40 is an overview block diagram of those
signals originating at the DC357 CMCTL Memory System Controller.


OK, thanks, that's great. Now I won't have to bother tracing things out if I 
decide to go that route. Didn't realize there was a printset for the KA650, but 
I guess I didn't even bother to check.

Re: KA650 VAX memory error

[Glen Slick via cctalk]

On Sat, Mar 2, 2019 at 12:02 PM Joseph Zatarski via cctalk
 wrote:
>
> On a somewhat related note, I don't suppose anybody knows or has
> documentation on the pinout of the C/D interconnect on these RAM boards?
> The pinout for the ribbon cable is in the manual, but the C/D
> interconnect doesn't seem to be documented in any of the manuals that
> are online.

650QS Field Maintenance Print Set, MP-02538-01, Rev C1
http://www.bitsavers.org/pdf/dec/vax/650/MP02538_650QS_Sep88.pdf

Page 65 of the PDF, KA650 Circuit Schematics Page 23 of 40
MA0 - MA9
CAS0 - CAS3
RAS0 - RAS3
WE
SE
XADDR20, XADDR21
+5
GND

Page 47 of the PDF, Page 5 of 40 is an overview block diagram of those
signals originating at the DC357 CMCTL Memory System Controller.

KA650 VAX memory error

[Joseph Zatarski via cctalk]

Hello Everyone,


I've got a KA650 with a MS650-AA 8MB memory module. When we initially 
started messing with this VAX, it was giving a memory error. We were 
able to track down first the bad bank, and later the individual bad ZIP 
RAMs with the help of my logic analyzer. For now, I kludged an SOJ DRAM 
in there that seems to be working without issue. The machine no longer 
gives memory errors during POST, but if you run one of the more thorough 
memory tests like #48 (MEM_Addr_shrts), it fails. My initial thought was 
that this RAM test checks for shorted address lines, which would cause 
writing to one location to change another location perhaps. However, I 
haven't been able to replicate the error with DEPOSITs and EXAMINEs on 
the console.



Without having to disassemble the VAX ROM, does anybody know what this 
test does? Once I know what I'm looking for, I can probably convince the 
logic analyzer to see the error with some fancy triggering, and get this 
board 100% fixed before I order some ZIP DRAMs.



On a somewhat related note, I don't suppose anybody knows or has 
documentation on the pinout of the C/D interconnect on these RAM boards? 
The pinout for the ribbon cable is in the manual, but the C/D 
interconnect doesn't seem to be documented in any of the manuals that 
are online. With the price of MS650's these days, it seems like the 
cheaper route (albeit more work) is to build a new RAM board rather than 
buy one (especially if a single 64MB board could be made). I suspect 
it's not too complex anyway, and it can probably mostly be traced out, 
and the rest inferred and then verified with a logic analyzer.



Thanks,

Joe Zatarski