On Thu, Jul 11, 2019, 12:31 Noel Chiappa via cctalk
wrote:
> it's also possible that
> since the -PA to -PV involved a faster clock, I wonder if some backplane
> lines turned into twisted pair, or coax?
PA used 25 MHz (40 ns cycle). PV and PW used 33 MHz (33.3 ns cycle). I
don't think PA to PV
> From: Eric Smith
> two separate backplanes that are combined for the RH20s (if
> present), one backplane for the A through D positions (upper 2/3 of
> each module slot), and one for E and F.
How odd. DEC was quite happy to do hex backplanes elsewhere, and it looks
from the
On Tue, Jul 9, 2019 at 4:44 PM Noel Chiappa via cctalk <
cctalk@classiccmp.org> wrote:
> Could an -A be upgraded to a -B by swapping the I/O backplane?
Electrically, yes, but physically it might not be easy. The portions of the
chassis that support the backplanes are different, and the power
> Erom: Eric Smith
Hey, thanks for taking the time to provide all those details.
As you no doubt saw, our emails crossed; I had managed to work out my own
what the difference was. I'd been looking at this page:
http://corestore.org/DEC2065.htm
and saw the two backplanes, and assumed one
> So my new theory is that it's the MBox (either the backplane, the
> boards, or the wiring from it to connectors, etc) that is the difference
> between the KL10-A and the KL10-B.
So I wuz confused; the second backplane is not the MBox (which is apparently
on the main CPU backplane),
On Mon, Jul 8, 2019 at 1:30 PM Noel Chiappa via cctalk <
cctalk@classiccmp.org> wrote:
> So early KL10's (KL10-A's, to be precise) only support a single DTE20, and
> no RH20's. Later ones supported up to 4 of the former, and up to 8 of the
> latter.
>
That's because the 1080 has different I/O
