Author: mcrosier Date: Thu Nov 14 16:02:24 2013 New Revision: 194732 URL: http://llvm.org/viewvc/llvm-project?rev=194732&view=rev Log: [AArch64] Add support for legacy AArch32 NEON scalar shift right by immediate and accumulate instructions.
Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=194732&r1=194731&r2=194732&view=diff ============================================================================== --- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original) +++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Thu Nov 14 16:02:24 2013 @@ -2913,10 +2913,21 @@ Value *CodeGenFunction::EmitAArch64Built : Intrinsic::aarch64_neon_vsrshr; return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrshr_n"); case AArch64::BI__builtin_neon_vsra_n_v: + if (VTy->getElementType()->isIntegerTy(64)) { + Int = usgn ? Intrinsic::aarch64_neon_vsradu_n + : Intrinsic::aarch64_neon_vsrads_n; + return EmitNeonCall(CGM.getIntrinsic(Int), Ops, "vsra_n"); + } return EmitARMBuiltinExpr(ARM::BI__builtin_neon_vsra_n_v, E); case AArch64::BI__builtin_neon_vsraq_n_v: return EmitARMBuiltinExpr(ARM::BI__builtin_neon_vsraq_n_v, E); case AArch64::BI__builtin_neon_vrsra_n_v: + if (VTy->getElementType()->isIntegerTy(64)) { + Int = usgn ? Intrinsic::aarch64_neon_vrsradu_n + : Intrinsic::aarch64_neon_vrsrads_n; + return EmitNeonCall(CGM.getIntrinsic(Int), Ops, "vrsra_n"); + } + // fall through case AArch64::BI__builtin_neon_vrsraq_n_v: { Ops[0] = Builder.CreateBitCast(Ops[0], Ty); Ops[1] = Builder.CreateBitCast(Ops[1], Ty); Modified: cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c?rev=194732&r1=194731&r2=194732&view=diff ============================================================================== --- cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c (original) +++ cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c Thu Nov 14 16:02:24 2013 @@ -7538,24 +7538,48 @@ int64_t test_vsrad_n_s64(int64_t a, int6 return (int64_t)vsrad_n_s64(a, b, 63); } +int64x1_t test_vsra_n_s64(int64x1_t a, int64x1_t b) { +// CHECK: test_vsra_n_s64 +// CHECK: ssra d{{[0-9]+}}, d{{[0-9]+}}, #1 + return vsra_n_s64(a, b, 1); +} + uint64_t test_vsrad_n_u64(uint64_t a, uint64_t b) { // CHECK-LABEL: test_vsrad_n_u64 // CHECK: usra {{d[0-9]+}}, {{d[0-9]+}}, #63 return (uint64_t)vsrad_n_u64(a, b, 63); } +uint64x1_t test_vsra_n_u64(uint64x1_t a, uint64x1_t b) { +// CHECK: test_vsra_n_u64 +// CHECK: usra d{{[0-9]+}}, d{{[0-9]+}}, #1 + return vsra_n_u64(a, b, 1); +} + int64_t test_vrsrad_n_s64(int64_t a, int64_t b) { // CHECK-LABEL: test_vrsrad_n_s64 // CHECK: srsra {{d[0-9]+}}, {{d[0-9]+}}, #63 return (int64_t)vrsrad_n_s64(a, b, 63); } +int64x1_t test_vrsra_n_s64(int64x1_t a, int64x1_t b) { +// CHECK: test_vrsra_n_s64 +// CHECK: srsra d{{[0-9]+}}, d{{[0-9]+}}, #1 + return vrsra_n_s64(a, b, 1); +} + uint64_t test_vrsrad_n_u64(uint64_t a, uint64_t b) { // CHECK-LABEL: test_vrsrad_n_u64 // CHECK: ursra {{d[0-9]+}}, {{d[0-9]+}}, #63 return (uint64_t)vrsrad_n_u64(a, b, 63); } +uint64x1_t test_vrsra_n_u64(uint64x1_t a, uint64x1_t b) { +// CHECK: test_vrsra_n_u64 +// CHECK: ursra d{{[0-9]+}}, d{{[0-9]+}}, #1 + return vrsra_n_u64(a, b, 1); +} + int64_t test_vshld_n_s64(int64_t a) { // CHECK-LABEL: test_vshld_n_s64 // CHECK: shl {{d[0-9]+}}, {{d[0-9]+}}, #0 _______________________________________________ cfe-commits mailing list cfe-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits