https://github.com/balazske approved this pull request.
https://github.com/llvm/llvm-project/pull/74991
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@@ -0,0 +1,50 @@
+// REQUIRES: !system-windows
+
+// RUN: rm -rf %t
+// RUN: split-file %s %t
+// RUN: cd %t
+//
+// RUN: %clang_cc1 -std=c++20 %t/layer1.cppm -triple %itanium_abi_triple \
+// RUN: -emit-module-interface -o %t/foo-layer1.pcm
+// RUN: %clang_cc1 -std=c++20
https://github.com/ChuanqiXu9 updated
https://github.com/llvm/llvm-project/pull/75912
>From 908a0287e092ce7ac1865de32370ec3114b104ad Mon Sep 17 00:00:00 2001
From: Chuanqi Xu
Date: Tue, 19 Dec 2023 17:00:59 +0800
Subject: [PATCH] [C++20] [Modules] [Itanium ABI] Generate the vtable in the
vvereschaka wrote:
not a problem, I'll land this patch,
https://github.com/llvm/llvm-project/pull/75556
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vgvassilev wrote:
If all good, would you mind landing it? I need to disappear for couple of
hours.
https://github.com/llvm/llvm-project/pull/75556
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vvereschaka wrote:
I would like to do a full rebuild just in case. I'll let you know about the
results.
https://github.com/llvm/llvm-project/pull/75556
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llvmbot wrote:
@llvm/pr-subscribers-clang-format
Author: Owen Pan (owenca)
Changes
This is needed because Windows doesn't have anything equivalent to the POSIX
fnmatch() function.
---
Full diff: https://github.com/llvm/llvm-project/pull/76021.diff
5 Files Affected:
- (modified)
vvereschaka wrote:
@vgvassilev thank you. This patch looks promising, the tests have been passed
successfully with it
```
-- Testing: 21 of 19608 tests, 21 workers --
PASS: Clang-Unit :: Interpreter/./ClangReplInterpreterTests.exe/8/21 (1 of 21)
PASS: Clang-Unit ::
https://github.com/owenca created
https://github.com/llvm/llvm-project/pull/76021
This is needed because Windows doesn't have anything equivalent to the POSIX
fnmatch() function.
>From b53c8b6c6d34857168d868d99c8d7ea7a69621eb Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Tue, 19 Dec 2023
https://github.com/hstk30-hw updated
https://github.com/llvm/llvm-project/pull/76007
>From 2991e9b990702b22f67b1d7a146605b1388cec87 Mon Sep 17 00:00:00 2001
From: hstk30-hw
Date: Wed, 20 Dec 2023 12:26:15 +0800
Subject: [PATCH] [Clang][Sema] Fix Wswitch-default bad warning in template
vgvassilev wrote:
Can you try this one:
```diff
diff --git a/clang/unittests/Interpreter/CodeCompletionTest.cpp
b/clang/unittests/Interpreter/CodeCompletionTest.cpp
index cd7fdfa588a5..873fbda32f05 100644
--- a/clang/unittests/Interpreter/CodeCompletionTest.cpp
+++
vgvassilev wrote:
I am testing a fix/workaround. Will send a diff shortly...
https://github.com/llvm/llvm-project/pull/75556
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vvereschaka wrote:
I also didn't noticed any related changes with the triple in these commits, but
they were the only related with the interpreter in the failed build. I just
tried to revert them and run these tests again.
https://github.com/llvm/llvm-project/pull/75556
dongjianqiang2 wrote:
thanks for correcting this.
https://github.com/llvm/llvm-project/pull/76007
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/75760
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vvereschaka wrote:
I tried to revert this commit and two next ones with the warning fixes (they
are related) locally on the builder. The tests have passed successfully after
reverting
These commits have been reverted
* 8c296d58c50902e367f64417948d6e2d43828f36
*
ecnelises wrote:
> Is there any existing vector test coverage?
Yes, there are vector tests in PowerPC's fminimum-fmaximum.ll.
https://github.com/llvm/llvm-project/pull/67301
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@@ -8262,6 +8262,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
+SelectionDAG ) const {
+ SDLoc DL(N);
+ SDValue LHS =
@@ -8262,6 +8262,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
+SelectionDAG ) const {
+ SDLoc DL(N);
+ SDValue LHS =
vgvassilev wrote:
@vvereschaka, would reverting this PR fix the problem? The error seems
unrelated to the code changes. IIUC it says that we fail to pass the correct
target triple to be able to execute code...
https://github.com/llvm/llvm-project/pull/75556
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67301
>From 92abb76631594dfc2ca586c46c38031610be0548 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:08:59 +0800
Subject: [PATCH 1/5] [Legalizer] Expand fmaximum and fminimum
According to
https://github.com/mariusz-sikora-at-amd closed
https://github.com/llvm/llvm-project/pull/68744
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@@ -216,6 +216,25 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280",
SiFive7Model,
[TuneSiFive7,
TuneDLenFactor2]>;
+def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel,
+
https://github.com/4vtomat closed
https://github.com/llvm/llvm-project/pull/75890
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Author: Brandon Wu
Date: 2023-12-20T14:42:11+08:00
New Revision: 379d32dab812731dc8883eff48477fd5cc7c8a17
URL:
https://github.com/llvm/llvm-project/commit/379d32dab812731dc8883eff48477fd5cc7c8a17
DIFF:
https://github.com/llvm/llvm-project/commit/379d32dab812731dc8883eff48477fd5cc7c8a17.diff
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/75890
>From 3f4a4f10ed75cb0b0f937129b2372184ac34849d Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Mon, 18 Dec 2023 15:52:14 +0800
Subject: [PATCH 1/2] Recommit [RISCV] Implement multi-lib reuse rule for
RISC-V
https://github.com/cor3ntin closed
https://github.com/llvm/llvm-project/pull/75913
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Author: cor3ntin
Date: 2023-12-20T07:41:24+01:00
New Revision: c8536760612785e8ee97a5261c20d22c6712b4b2
URL:
https://github.com/llvm/llvm-project/commit/c8536760612785e8ee97a5261c20d22c6712b4b2
DIFF:
https://github.com/llvm/llvm-project/commit/c8536760612785e8ee97a5261c20d22c6712b4b2.diff
@@ -216,6 +216,25 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280",
SiFive7Model,
[TuneSiFive7,
TuneDLenFactor2]>;
+def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel,
+
@@ -0,0 +1,50 @@
+// REQUIRES: !system-windows
+
+// RUN: rm -rf %t
+// RUN: split-file %s %t
+// RUN: cd %t
+//
+// RUN: %clang_cc1 -std=c++20 %t/layer1.cppm -triple %itanium_abi_triple \
+// RUN: -emit-module-interface -o %t/foo-layer1.pcm
+// RUN: %clang_cc1 -std=c++20
https://github.com/hstk30-hw updated
https://github.com/llvm/llvm-project/pull/76007
>From 7b8c1c758c77550536b9d16027b2e51090e365be Mon Sep 17 00:00:00 2001
From: hstk-hw
Date: Wed, 20 Dec 2023 12:26:15 +0800
Subject: [PATCH]in templates. This PR will address that.
---
ChipsSpectre wrote:
The Fork is now rebased on main, so the conflict in `ReleaseNotes.rst` is
resolved.
@tbaederr Do you think it is ready to be merged now?
https://github.com/llvm/llvm-project/pull/74926
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@@ -0,0 +1,50 @@
+// REQUIRES: !system-windows
+
+// RUN: rm -rf %t
+// RUN: split-file %s %t
+// RUN: cd %t
+//
+// RUN: %clang_cc1 -std=c++20 %t/layer1.cppm -triple %itanium_abi_triple \
+// RUN: -emit-module-interface -o %t/foo-layer1.pcm
+// RUN: %clang_cc1 -std=c++20
https://github.com/ChipsSpectre updated
https://github.com/llvm/llvm-project/pull/74926
>From a08d9029445087b78d19715991c426106d9b0ca6 Mon Sep 17 00:00:00 2001
From: ChipsSpectre
Date: Wed, 20 Dec 2023 07:33:20 +0100
Subject: [PATCH] [clang][Parse] `TryAnnotateCXXScopeToken` to be called only
@@ -0,0 +1,50 @@
+// REQUIRES: !system-windows
+
+// RUN: rm -rf %t
+// RUN: split-file %s %t
+// RUN: cd %t
+//
+// RUN: %clang_cc1 -std=c++20 %t/layer1.cppm -triple %itanium_abi_triple \
+// RUN: -emit-module-interface -o %t/foo-layer1.pcm
+// RUN: %clang_cc1 -std=c++20
@@ -0,0 +1,50 @@
+// REQUIRES: !system-windows
+
+// RUN: rm -rf %t
+// RUN: split-file %s %t
+// RUN: cd %t
+//
+// RUN: %clang_cc1 -std=c++20 %t/layer1.cppm -triple %itanium_abi_triple \
+// RUN: -emit-module-interface -o %t/foo-layer1.pcm
+// RUN: %clang_cc1 -std=c++20
https://github.com/ChipsSpectre updated
https://github.com/llvm/llvm-project/pull/74926
>From 28a5e6ffab5ec5fef7edce58c4dbdebffcfaabe3 Mon Sep 17 00:00:00 2001
From: ChipsSpectre
Date: Tue, 19 Dec 2023 05:14:06 +0100
Subject: [PATCH] [clang][Parse] `TryAnnotateCXXScopeToken` to be called only
https://github.com/topperc updated
https://github.com/llvm/llvm-project/pull/75760
>From 22fd20164e9d061a451555c5158f0a8ecb73f77e Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Sun, 17 Dec 2023 18:18:43 -0800
Subject: [PATCH 1/3] [RISCV] Add sifive-p450 CPU.
This is an out of order core
https://github.com/H-G-Hristov updated
https://github.com/llvm/llvm-project/pull/74994
>From 6e26ca239c49e1b7d9ab72217db7339e92df163f Mon Sep 17 00:00:00 2001
From: Zingam
Date: Sun, 10 Dec 2023 14:16:02 +0200
Subject: [PATCH 01/17] [libc++][span] P2821R5: span.at()
---
libcxx/include/span
https://github.com/hstk30-hw edited
https://github.com/llvm/llvm-project/pull/76007
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vgvassilev wrote:
@vvereschaka, thanks for the ping. Will look into this shortly. Feel free to
revert.
https://github.com/llvm/llvm-project/pull/75556
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phoebewang wrote:
Thanks @MaxEW707 ! I don't have other comments now. Do you need help to merge
it for you?
https://github.com/llvm/llvm-project/pull/75992
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https://github.com/cjdb closed https://github.com/llvm/llvm-project/pull/75259
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cjdb wrote:
Merging, with the promise to diligently resolve post-commit feedback in early
January. Anything that's specific to this patch will be actioned before
starting work on the remaining fold algorithms, and anything that's generalised
to `std::ranges` will be actioned after finishing
https://github.com/KanRobert approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/75978
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https://github.com/MaskRay closed
https://github.com/llvm/llvm-project/pull/75889
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Author: Fangrui Song
Date: 2023-12-19T21:51:26-08:00
New Revision: 207cbbd71009090768c63004b967eddfab0f1d2e
URL:
https://github.com/llvm/llvm-project/commit/207cbbd71009090768c63004b967eddfab0f1d2e
DIFF:
https://github.com/llvm/llvm-project/commit/207cbbd71009090768c63004b967eddfab0f1d2e.diff
https://github.com/MaskRay closed
https://github.com/llvm/llvm-project/pull/75986
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Author: Fangrui Song
Date: 2023-12-19T21:51:05-08:00
New Revision: 47413bb2760e63a3302871ea770d6c0f5a742036
URL:
https://github.com/llvm/llvm-project/commit/47413bb2760e63a3302871ea770d6c0f5a742036
DIFF:
https://github.com/llvm/llvm-project/commit/47413bb2760e63a3302871ea770d6c0f5a742036.diff
@@ -222,6 +222,11 @@
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature"
"+zvl64b"
// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1
-menable-experimental-extensions -mcpu=sifive-p450 | FileCheck
vvereschaka wrote:
Looks like these changes break the`ClangReplInterpreterTests` unit tests
* https://lab.llvm.org/buildbot/#/builders/119/builds/16346
* https://lab.llvm.org/buildbot/#/builders/60/builds/15188
* Clang-Unit :: Interpreter/./ClangReplInterpreterTests.exe/17/21
* Clang-Unit ::
https://github.com/srcarroll updated
https://github.com/llvm/llvm-project/pull/76003
>From 860a2f794bdf12ff1f08d4802570757e805264b0 Mon Sep 17 00:00:00 2001
From: Sam
Date: Mon, 18 Dec 2023 15:53:41 -0600
Subject: [PATCH 1/8] [mlir][Linalg] Support dynamic sizes in `lower_pack`
transform
---
srcarroll wrote:
The current implementation will emit a `tensor.reshape` op if any of the dims
of the input are not factorable (require more than one dynamic dim in the
expansion). However, I could instead only emit reshapes for the dims that need
it, and then a `tensor.expand_shape` on the
https://github.com/shafik commented:
We should add a release note for this change.
https://github.com/llvm/llvm-project/pull/75135
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https://github.com/srcarroll edited
https://github.com/llvm/llvm-project/pull/76003
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https://github.com/srcarroll updated
https://github.com/llvm/llvm-project/pull/76003
>From 860a2f794bdf12ff1f08d4802570757e805264b0 Mon Sep 17 00:00:00 2001
From: Sam
Date: Mon, 18 Dec 2023 15:53:41 -0600
Subject: [PATCH 1/7] [mlir][Linalg] Support dynamic sizes in `lower_pack`
transform
---
https://github.com/srcarroll edited
https://github.com/llvm/llvm-project/pull/76003
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https://github.com/llvm/llvm-project/pull/76003
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@@ -0,0 +1,27 @@
+// RUN: %clang_cc1 -fsyntax-only -verify -std=c++11 -Wswitch-default %s
shafik wrote:
I think we can add these test to `clang/test/Sema/switch-default.c`
https://github.com/llvm/llvm-project/pull/76007
https://github.com/srcarroll updated
https://github.com/llvm/llvm-project/pull/76003
>From 860a2f794bdf12ff1f08d4802570757e805264b0 Mon Sep 17 00:00:00 2001
From: Sam
Date: Mon, 18 Dec 2023 15:53:41 -0600
Subject: [PATCH 1/7] [mlir][Linalg] Support dynamic sizes in `lower_pack`
transform
---
shafik wrote:
Can you add more details to you summary
"https://github.com/llvm/llvm-project/pull/73077 added -Wswitch-default
diagnostic but it produced false positives in templates. This PR will address
that issue"
https://github.com/llvm/llvm-project/pull/76007
https://github.com/srcarroll updated
https://github.com/llvm/llvm-project/pull/76003
>From 860a2f794bdf12ff1f08d4802570757e805264b0 Mon Sep 17 00:00:00 2001
From: Sam
Date: Mon, 18 Dec 2023 15:53:41 -0600
Subject: [PATCH 1/7] [mlir][Linalg] Support dynamic sizes in `lower_pack`
transform
---
@@ -1089,7 +1089,7 @@ collapseOpIterationDims(LinalgType op,
struct LowerPackResult {
tensor::PadOp padOp;
- tensor::ExpandShapeOp expandShapeOp;
+ Operation *expandShapeOp;
srcarroll wrote:
Not actually sure what would be appropriate here.
zyn0217 wrote:
> Maybe this deserves a new issue for clang Sema?
Sounds reasonable to me. Feel free to put up a PR / issue for this if you are
interested.
https://github.com/llvm/llvm-project/pull/75937
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@@ -1515,6 +1515,15 @@ def : Pat<(X86add_flag_nocf GR32:$src1, 128),
def : Pat<(X86add_flag_nocf GR64:$src1, 128),
(SUB64ri32 GR64:$src1, -128)>;
+// Depositing value to 8/16 bit subreg:
+def : Pat<(or (and GR64:$dst, -256),
+ (i64 (zextloadi8
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
--check-prefixes=X64
+
+define i64 @sub8(i64 noundef %res, ptr %byte) {
+; X64-LABEL: sub8:
+;
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
--check-prefixes=X64
david-xl wrote:
Done.
x64 is used elsewhere too. Anyway
https://github.com/srcarroll updated
https://github.com/llvm/llvm-project/pull/76003
>From 860a2f794bdf12ff1f08d4802570757e805264b0 Mon Sep 17 00:00:00 2001
From: Sam
Date: Mon, 18 Dec 2023 15:53:41 -0600
Subject: [PATCH 1/6] [mlir][Linalg] Support dynamic sizes in `lower_pack`
transform
---
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (hstk30-hw)
Changes
Fix https://github.com/llvm/llvm-project/issues/75943
---
Full diff: https://github.com/llvm/llvm-project/pull/76007.diff
2 Files Affected:
- (modified) clang/lib/Sema/SemaStmt.cpp (+1-3)
- (added)
https://github.com/hstk30-hw created
https://github.com/llvm/llvm-project/pull/76007
Fix https://github.com/llvm/llvm-project/issues/75943
>From c3d5ac42726c49fd7036972042eb70d3e5dc01a6 Mon Sep 17 00:00:00 2001
From: hstk-hw
Date: Wed, 20 Dec 2023 12:26:15 +0800
Subject: [PATCH] fix: fix
https://github.com/srcarroll updated
https://github.com/llvm/llvm-project/pull/76003
>From 860a2f794bdf12ff1f08d4802570757e805264b0 Mon Sep 17 00:00:00 2001
From: Sam
Date: Mon, 18 Dec 2023 15:53:41 -0600
Subject: [PATCH 1/5] [mlir][Linalg] Support dynamic sizes in `lower_pack`
transform
---
minglotus-6 wrote:
And pushed https://github.com/llvm/llvm-project/pull/76005 to require 64-bit
systems for IR test. Raw profile reader swaps byte orders properly so
`REQUIRES: host-byteorder-little-endian` looks actually unnecessary but will
keep it fwiw for now.
I feel sorry for dance
@@ -121,38 +121,36 @@ entry:
declare
@llvm.riscv.sf.vqmaccus.4x8x4.nxv16i32.nxv8i8.nxv64i8(
,
,
- ,
+ ,
iXLen, iXLen);
-define @intrinsic_vqmaccus_4x8x4_tu_i32m8( %0, %1, %2, iXLen %3) nounwind {
+define @intrinsic_vqmaccus_4x8x4_tu_i32m8( %0, %1, %2, iXLen
https://github.com/topperc edited
https://github.com/llvm/llvm-project/pull/75760
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@@ -222,6 +222,11 @@
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature"
"+zvl64b"
// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1
-menable-experimental-extensions -mcpu=sifive-p450 | FileCheck
minglotus-6 wrote:
> I'm seeing spurious failures from big-endian systems. I'll revert and
> investigate a fix.
I ended up sending a fix forward in
https://github.com/llvm/llvm-project/pull/76001 . Will monitor the build-bots.
https://github.com/llvm/llvm-project/pull/75954
https://github.com/srcarroll created
https://github.com/llvm/llvm-project/pull/76003
When an expanded dim is not factorable, emit a `tensor.reshape` instead of a
`tensor.expand_shape`
>From 860a2f794bdf12ff1f08d4802570757e805264b0 Mon Sep 17 00:00:00 2001
From: Sam
Date: Mon, 18 Dec 2023
https://github.com/kkwli approved this pull request.
LG.
Please wait for a day or two to see if other reviewers have any comments.
Thanks.
https://github.com/llvm/llvm-project/pull/75921
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Lancern wrote:
> The place you're patching is not only specific to "completing override
> functions", but handles all completion strings involving function
> declarations.
OK. I'll move the changes to the
`CodeCompletionResult::createCodeCompletionStringForOverride` function which
seems
frobtech wrote:
The meaning that we want to make clear is that this toggles the special
behavior of forcing the visibility of these symbols despite all the other
mechanisms that usually control visibility for all other symbols. So perhaps
`-fforced-global-new-delete-visibility` (or even
minglotus-6 wrote:
I'm seeing spurious failures from big-endian systems. I'll revert and
investigate a fix.
https://github.com/llvm/llvm-project/pull/75954
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https://github.com/silver-popov updated
https://github.com/llvm/llvm-project/pull/75909
>From 00edd52687d6e15f3453912b5dbf236714a386f9 Mon Sep 17 00:00:00 2001
From: Igor Popov
Date: Tue, 19 Dec 2023 11:43:45 +0300
Subject: [PATCH] Remove wrong float-128 extension for CLang
---
@@ -561,6 +561,16 @@ def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins
i64mem:$src),
[(set GR64:$dst, (load addr:$src))]>;
}
+def : Pat<(or (and GR64:$dst, -256),
david-xl wrote:
Sorry I misunderstood. Fixed now.
Also updated the
@@ -222,6 +222,11 @@
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature"
"+zvl64b"
// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1
-menable-experimental-extensions -mcpu=sifive-p450 | FileCheck
@@ -222,6 +222,11 @@
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature"
"+zvl64b"
// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1
-menable-experimental-extensions -mcpu=sifive-p450 | FileCheck
https://github.com/MaxEW707 edited
https://github.com/llvm/llvm-project/pull/75992
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@@ -580,8 +580,7 @@ _storebe_i64(void * __P, long long __D) {
#include
#endif
-/* Some intrinsics inside adxintrin.h are available only on processors with
ADX,
- * whereas others are also available at all times. */
MaxEW707 wrote:
Confirmed that Intel ADX
zyn0217 wrote:
Bonus: It appears that neither gcc nor clang implements a provision change from
[CWG1351](https://cplusplus.github.io/CWG/issues/1351.html),
> [except.spec]p4
> ..., **unless the overriding function is defined as deleted.**
giving errors on the following code.
```cpp
struct B
https://github.com/MaxEW707 updated
https://github.com/llvm/llvm-project/pull/75992
>From b6ea2ffe22f414ec79cd9ccd7e47c7b063583bcc Mon Sep 17 00:00:00 2001
From: MaxEW707 <82551778+maxew...@users.noreply.github.com>
Date: Tue, 19 Dec 2023 19:55:21 -0500
Subject: [PATCH 1/4] Move Intel ADC
@@ -580,8 +580,7 @@ _storebe_i64(void * __P, long long __D) {
#include
#endif
-/* Some intrinsics inside adxintrin.h are available only on processors with
ADX,
- * whereas others are also available at all times. */
phoebewang wrote:
I think comment is
https://github.com/MaxEW707 edited
https://github.com/llvm/llvm-project/pull/75992
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https://github.com/dongjianqiang2 closed
https://github.com/llvm/llvm-project/pull/75900
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Author: hstk30-hw
Date: 2023-12-20T10:26:27+08:00
New Revision: e5eef6e24f06dfffc77cffc6963e8543f9d223bd
URL:
https://github.com/llvm/llvm-project/commit/e5eef6e24f06dfffc77cffc6963e8543f9d223bd
DIFF:
https://github.com/llvm/llvm-project/commit/e5eef6e24f06dfffc77cffc6963e8543f9d223bd.diff
ChuanqiXu9 wrote:
Yeah, it'll be much better if we had that feature.
https://github.com/llvm/llvm-project/pull/71622
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https://github.com/MaxEW707 edited
https://github.com/llvm/llvm-project/pull/75992
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https://github.com/MaxEW707 edited
https://github.com/llvm/llvm-project/pull/75992
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https://github.com/MaxEW707 edited
https://github.com/llvm/llvm-project/pull/75992
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