https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/77608
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@@ -0,0 +1,80 @@
+; RUN: llc -mtriple=x86_64-pc-windows-msvc %s
e-kud wrote:
It seems we still have this file on `avx512-intel64` worker:
https://lab.llvm.org/buildbot/#/builders/258/builds/12970
https://lab.llvm.org/buildbot/#/builders/258/builds/12971
https://github.com/e-kud closed https://github.com/llvm/llvm-project/pull/79088
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https://github.com/e-kud updated https://github.com/llvm/llvm-project/pull/79088
>From 8ba23b70c07f21be03102b2975046ca9a5afb90b Mon Sep 17 00:00:00 2001
From: Evgenii Kudriashov
Date: Mon, 22 Jan 2024 18:00:19 -0800
Subject: [PATCH] [X86][GlobalISel] Remove G_OR/G_AND/G_XOR test duplication
https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/77925
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https://github.com/e-kud approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/77925
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@@ -3963,6 +3963,60 @@ implicitly included in later levels.
- ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA,
LZCNT, MOVBE, XSAVE
- ``-march=x86-64-v4``: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL
+`Intel AVX10 ISA
https://github.com/e-kud edited https://github.com/llvm/llvm-project/pull/77925
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@@ -3963,6 +3963,60 @@ implicitly included in later levels.
- ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA,
LZCNT, MOVBE, XSAVE
- ``-march=x86-64-v4``: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL
+`Intel AVX10 ISA
@@ -3963,6 +3963,60 @@ implicitly included in later levels.
- ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA,
LZCNT, MOVBE, XSAVE
- ``-march=x86-64-v4``: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL
+`Intel AVX10 ISA
e-kud wrote:
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/75571
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https://github.com/e-kud approved this pull request.
Interesting. LGTM
https://github.com/llvm/llvm-project/pull/72126
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https://github.com/e-kud approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/71318
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e-kud wrote:
I'm a little bit confused, What's the expected behavior of `+avx10.1-512
-avx10.1-256` in codegen aspect. Should we generate only instructions in the
difference of sets? Or do we consider `avx10.1-256` as a base of `avx10.1-512`
and if it is disabled `avx10.1-512` can't be
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (Feature.substr(0, 7) == "+avx10.") {
- HasAVX10 = true;
- HasAVX512F = true;
- if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
- }
https://github.com/e-kud approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/67278
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https://github.com/e-kud approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/67278
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https://github.com/e-kud approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/67278
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@@ -130,17 +131,35 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (!HasAVX512F && Feature.substr(0, 7) == "+avx512")
+if (Feature.substr(0, 7) == "+avx10.") {
+ HasAVX10 = true;
HasAVX512F = true;
-if (HasAVX512F && Feature ==
@@ -130,17 +131,35 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (!HasAVX512F && Feature.substr(0, 7) == "+avx512")
+if (Feature.substr(0, 7) == "+avx10.") {
+ HasAVX10 = true;
HasAVX512F = true;
-if (HasAVX512F && Feature ==
@@ -130,17 +131,35 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (!HasAVX512F && Feature.substr(0, 7) == "+avx512")
+if (Feature.substr(0, 7) == "+avx10.") {
+ HasAVX10 = true;
HasAVX512F = true;
-if (HasAVX512F && Feature ==
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