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https://github.com/llvm/llvm-project/pull/132489
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jrtc27 wrote:
> I'm mostly concerned about the case where the lowered node has the wrong
> type. For example, AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN always
> creates a value with the pointer width of addrspace 0, but address spaces
> exist which don't have the native pointer width (arm
https://github.com/jrtc27 updated
https://github.com/llvm/llvm-project/pull/132489
>From 778502b697d7fe547e827f7d7394a7013a1c9ffb Mon Sep 17 00:00:00 2001
From: Jessica Clarke
Date: Fri, 21 Mar 2025 23:15:23 +
Subject: [PATCH 1/2] [clang][IR] Overload @llvm.thread.pointer to support
non-AS
https://github.com/jrtc27 updated
https://github.com/llvm/llvm-project/pull/132489
>From 778502b697d7fe547e827f7d7394a7013a1c9ffb Mon Sep 17 00:00:00 2001
From: Jessica Clarke
Date: Fri, 21 Mar 2025 23:15:23 +
Subject: [PATCH 1/3] [clang][IR] Overload @llvm.thread.pointer to support
non-AS
jrtc27 wrote:
Is there a reason why these aren't lowercase like the rest?
https://github.com/llvm/llvm-project/pull/132481
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https://github.com/llvm/llvm-project/pull/132489
Thraed-local globals live, by default, in the default globals address
space, which may not be 0, so we need to overload @llvm.thread.pointer
to support other address spaces, and use the default globals address
spa
jrtc27 wrote:
> I think you also need to fix the backends so if they see thread_pointer
> intrinsic with the wrong address-space, they don't crash.
I don't believe they do crash? At least, I can't construct IR using any
addrspace (even some of the special X86 ones) that makes amd64/aarch64/ris
jrtc27 wrote:
Ping
https://github.com/llvm/llvm-project/pull/132489
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jrtc27 wrote:
Although C++ might have good alternatives, that's not so helpful for C headers
being included from C++ that might end up using this (e.g. some static inline
function in a system header).
https://github.com/llvm/llvm-project/pull/133125
https://github.com/jrtc27 edited
https://github.com/llvm/llvm-project/pull/132489
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jrtc27 wrote:
As far as I know GPUs don't do TLS...
https://github.com/llvm/llvm-project/pull/132489
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jrtc27 wrote:
Is this the kind of thing we have agreed to take in LLVM? If it's "simulation
hint" instructions, does that not by definition mean that it's not an extension
present in real hardware?
https://github.com/llvm/llvm-project/pull/128833
___
@@ -202,6 +202,7 @@
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large
Offset Load Store Extension)
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load
Store Multiple Extension)
// CHECK-NEXT: xqcisls 0.2
@@ -452,12 +452,12 @@ void FreeBSD::addLibCxxIncludePaths(const
llvm::opt::ArgList &DriverArgs,
void FreeBSD::AddCXXStdlibLibArgs(const ArgList &Args,
ArgStringList &CmdArgs) const {
+ Generic_ELF::AddCXXStdlibLibArgs(Args, CmdArgs);
unsi
@@ -464,6 +464,7 @@ static void parseTargetArgs(TargetOptions &opts,
llvm::opt::ArgList &args) {
if (const llvm::opt::Arg *a =
args.getLastArg(clang::driver::options::OPT_mabi_EQ)) {
+opts.abi = a->getValue();
llvm::StringRef V = a->getValue();
if (V
@@ -62,6 +62,15 @@ static cl::opt RISCVMinimumJumpTableEntries(
"riscv-min-jump-table-entries", cl::Hidden,
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+static cl::opt
+UseLoadStorePairsOpt("riscv-load-store-pairs",
jrt
jrtc27 wrote:
> Side note: my motivation in removing StringLiteral is that it is a bit of a
> footgun. While the original https://reviews.llvm.org/D27686 clearly states
> that it's intended for arrays of string literals, where it would not be
> possible anyway to store each literal as a true l
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
jrtc27 wrote:
> I had to do something very similar for CHERI downstream: We have to ensure
> that all globals are precisely representable (which may require rounding up
> the size+alignment) so you don't end up creating bounds that include adjacent
> ones. The original patch from 2019 is here:
@@ -78,6 +78,19 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
// to change to the appropriate rv32/rv64 version.
def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>,
GenericTuneInfo;
+def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
+
@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64;
static const int16_t cSledLength = 8;
#elif defined(__hexagon__)
static const int16_t cSledLength = 20;
+#elif SANITIZER_RISCV64
+static const int16_t cSledLength = 76;
+#elif defined(__riscv) && (__riscv_xlen == 32)
---
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
jrtc27 wrote:
Extensions belong in their own PRs, ditto CPU/scheduler, driver and any
additional passes. Each PR is one commit and this is not one commit's worth of
changes.
https://github.com/llvm/llvm-project/pull/117865
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@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
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@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64;
static const int16_t cSledLength = 8;
#elif defined(__hexagon__)
static const int16_t cSledLength = 20;
+#elif SANITIZER_RISCV64
+static const int16_t cSledLength = 76;
+#elif defined(__riscv) && (__riscv_xlen == 32)
---
@@ -1103,7 +1103,15 @@ static void InitializePredefinedMacros(const TargetInfo
&TI,
assert(TI.getCharWidth() == 8 && "Only support 8-bit char so far");
Builder.defineMacro("__CHAR_BIT__", Twine(TI.getCharWidth()));
- Builder.defineMacro("__BOOL_WIDTH__", Twine(TI.getBool
@@ -1103,7 +1103,15 @@ static void InitializePredefinedMacros(const TargetInfo
&TI,
assert(TI.getCharWidth() == 8 && "Only support 8-bit char so far");
Builder.defineMacro("__CHAR_BIT__", Twine(TI.getCharWidth()));
- Builder.defineMacro("__BOOL_WIDTH__", Twine(TI.getBool
@@ -0,0 +1,27 @@
+// RUN: %clang_cc1 -verify -std=c23 -ffreestanding %s
+
+/* WG14 N2412: Clang 14
+ * Two's complement sign representation
+ */
+// expected-no-diagnostics
+
+#include
+
+// GH117348 -- BOOL_WIDTH was accidentally expanding to the number of bits in
+// the object
jrtc27 wrote:
> Considering the define is guarded behind `if
> (ISAInfo->hasExtension("zve32x"))`, this doesn't seem to implement:
> [riscv-non-isa/rvv-intrinsic-doc#382](https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/382)
Presumably that (rather terse) sentence in the specification i
jrtc27 wrote:
I disagree that this is a thing which should exist. It's solving the problem in
the wrong place.
https://github.com/llvm/llvm-project/pull/115981
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https://github.com/llvm/llvm-project/pull/113732
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@@ -280,14 +280,18 @@ static void initRISCVFeature(struct riscv_hwprobe
Hwprobes[]) {
static int FeaturesBitCached = 0;
-void __init_riscv_feature_bits() CONSTRUCTOR_ATTRIBUTE;
+void __init_riscv_feature_bits(void *) CONSTRUCTOR_ATTRIBUTE;
// A constructor function that s
@@ -280,14 +280,18 @@ static void initRISCVFeature(struct riscv_hwprobe
Hwprobes[]) {
static int FeaturesBitCached = 0;
-void __init_riscv_feature_bits() CONSTRUCTOR_ATTRIBUTE;
+void __init_riscv_feature_bits(void *) CONSTRUCTOR_ATTRIBUTE;
// A constructor function that s
jrtc27 wrote:
> > "[LLVM] Trim intrinsics" is not a helpful commit message. What exactly are
> > you trying to achieve and why? Is there an RFC for this given it seems to
> > be having significant consequences across the tree?
>
> Yes, please see here:
> https://discourse.llvm.org/t/rfc-compr
jrtc27 wrote:
"[LLVM] Trim intrinsics" is not a helpful commit message. What exactly are you
trying to achieve and why? Is there an RFC for this given it seems to be having
significant consequences across the tree?
https://github.com/llvm/llvm-project/pull/112791
__
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
jrtc27 wrote:
This seems wrong. Emitting LLVM from the Clang frontend should not require
anything about the set of targets enabled in LLVM itself.
https://github.com/llvm/llvm-project/pull/112791
_
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https://github.com/llvm/llvm-project/pull/112791
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jrtc27 wrote:
@awilfox Could you please verify if this fixes the bug for you?
https://github.com/llvm/llvm-project/pull/112927
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https://github.com/llvm/llvm-project/pull/112927
>From 4f37ed5ff6c18c8cf0de244bb064d5f4f60065a4 Mon Sep 17 00:00:00 2001
From: Jessica Clarke
Date: Fri, 18 Oct 2024 16:50:22 +0100
Subject: [PATCH 1/2] [clang] Make LazyOffsetPtr more portable
LazyOffsetPtr curr
jrtc27 wrote:
> One style nit, otherwise looks good, thanks!
I'm not sure "good" is quite the right word given the horrors this interface is
hiding, but thanks for the review!
https://github.com/llvm/llvm-project/pull/112927
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https://github.com/llvm/llvm-project/pull/112927
LazyOffsetPtr currently relies on uint64_t being able to store a pointer
and, unless sizeof(uint64_t) == sizeof(void *), little endianness, since
getAddressOfPointer reinterprets the memory as a pointer. This also
jrtc27 wrote:
> > But yes, the short answer is that the code as written should work on
> > Morello and CHERI-RISC-V.
>
> Great, thanks.
>
> > > > The std::launder may be unnecessary
> > >
> > >
> > > Formally I think it's correct and necessary for the pointer and integer
> > > case because
jrtc27 wrote:
> > How about:
> > [...]
>
> Yeah, I think that fixes it. For me that looks a lot less simple than using a
> union, but it is nice to have only a single implementation. I'd be fine with
> going in that direction.
>
> For CHERI, can we assume that the least-significant byte of th
@@ -321,50 +322,87 @@ class ExternalASTSource : public
RefCountedBase {
/// external AST source itself.
template
struct LazyOffsetPtr {
- /// Either a pointer to an AST node or the offset within the
- /// external AST source where the AST node can be found.
- ///
- /// If
https://github.com/jrtc27 edited
https://github.com/llvm/llvm-project/pull/112806
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jrtc27 wrote:
> > > > #112806 should address this without narrowing the field to 32 bits.
> > >
> > >
> > > As does [#111995
> > > (comment)](https://github.com/llvm/llvm-project/pull/111995#discussion_r1805329590),
> > > with less code and more generality
> >
> >
> > I prefer this solution
@@ -321,50 +322,87 @@ class ExternalASTSource : public
RefCountedBase {
/// external AST source itself.
template
struct LazyOffsetPtr {
- /// Either a pointer to an AST node or the offset within the
- /// external AST source where the AST node can be found.
- ///
- /// If
jrtc27 wrote:
> #112806 should address this without narrowing the field to 32 bits.
As does
https://github.com/llvm/llvm-project/pull/111995#discussion_r1805329590, with
less code and more generality
https://github.com/llvm/llvm-project/pull/111995
@@ -326,25 +326,25 @@ struct LazyOffsetPtr {
///
/// If the low bit is clear, a pointer to the AST node. If the low
/// bit is set, the upper 63 bits are the offset.
- mutable uint64_t Ptr = 0;
+ mutable uintptr_t Ptr = 0;
public:
LazyOffsetPtr() = default;
- exp
https://github.com/jrtc27 edited
https://github.com/llvm/llvm-project/pull/111995
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@@ -326,25 +326,25 @@ struct LazyOffsetPtr {
///
/// If the low bit is clear, a pointer to the AST node. If the low
/// bit is set, the upper 63 bits are the offset.
- mutable uint64_t Ptr = 0;
+ mutable uintptr_t Ptr = 0;
public:
LazyOffsetPtr() = default;
- exp
@@ -326,25 +326,25 @@ struct LazyOffsetPtr {
///
/// If the low bit is clear, a pointer to the AST node. If the low
/// bit is set, the upper 63 bits are the offset.
- mutable uint64_t Ptr = 0;
+ mutable uintptr_t Ptr = 0;
public:
LazyOffsetPtr() = default;
- exp
https://github.com/jrtc27 edited
https://github.com/llvm/llvm-project/pull/111995
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@@ -326,25 +326,25 @@ struct LazyOffsetPtr {
///
/// If the low bit is clear, a pointer to the AST node. If the low
/// bit is set, the upper 63 bits are the offset.
- mutable uint64_t Ptr = 0;
+ mutable uintptr_t Ptr = 0;
public:
LazyOffsetPtr() = default;
- exp
@@ -326,25 +326,25 @@ struct LazyOffsetPtr {
///
/// If the low bit is clear, a pointer to the AST node. If the low
/// bit is set, the upper 63 bits are the offset.
- mutable uint64_t Ptr = 0;
+ mutable uintptr_t Ptr = 0;
public:
LazyOffsetPtr() = default;
- exp
@@ -326,25 +326,25 @@ struct LazyOffsetPtr {
///
/// If the low bit is clear, a pointer to the AST node. If the low
/// bit is set, the upper 63 bits are the offset.
- mutable uint64_t Ptr = 0;
+ mutable uintptr_t Ptr = 0;
public:
LazyOffsetPtr() = default;
- exp
@@ -326,25 +326,25 @@ struct LazyOffsetPtr {
///
/// If the low bit is clear, a pointer to the AST node. If the low
/// bit is set, the upper 63 bits are the offset.
- mutable uint64_t Ptr = 0;
+ mutable uintptr_t Ptr = 0;
public:
LazyOffsetPtr() = default;
- exp
@@ -326,25 +326,25 @@ struct LazyOffsetPtr {
///
/// If the low bit is clear, a pointer to the AST node. If the low
/// bit is set, the upper 63 bits are the offset.
- mutable uint64_t Ptr = 0;
+ mutable uintptr_t Ptr = 0;
public:
LazyOffsetPtr() = default;
- exp
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@@ -2970,22 +2974,28 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
// (__riscv_feature_bits.features[i] & REQUIRED_BITMASK) ==
// REQUIRED_BITMASK
//
+// First, check __riscv_feature_bits.length <=
+// llvm::RISCVISAInfo::FeatureBitSize. This ensur
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64-unknown-elf -verify-machineinstrs < %s \
+; RUN: | FileCheck %s
+
+define void @foo(i64 %t) sspstrong {
jrtc27 w
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64-unknown-elf -verify-machineinstrs < %s \
+; RUN: | FileCheck %s
+
+define void @foo(i64 %t) sspstrong {
jrtc27 w
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64-unknown-elf -verify-machineinstrs < %s \
jrtc27 wrote:
This was previously linux-gnu not elf. If it works fine with
@@ -23,3 +26,9 @@ void bar(int x) {
// AARCH64: [[ATTR1]] = !{i32 1, !"stack-protector-guard", !"sysreg"}
// AARCH64: [[ATTR2]] = !{i32 1, !"stack-protector-guard-reg", !"sp_el0"}
// AARCH64: [[ATTR3]] = !{i32 1, !"stack-protector-guard-offset", i32 1024}
+
+// RISCV: !llvm.mod
jrtc27 wrote:
Same comments as -global
https://github.com/llvm/llvm-project/pull/108942
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@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -verify-machineinstrs < %s | \
+; RUN: FileCheck %s
+
+target triple = "riscv64-unknown-linux-gnu"
+
+define dso_local void @foo(i64 %t) local_unnamed
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -verify-machineinstrs < %s | \
+; RUN: FileCheck %s
+
+target triple = "riscv64-unknown-linux-gnu"
+
+define dso_local void @foo(i64 %t) local_unnamed
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -verify-machineinstrs < %s | \
+; RUN: FileCheck %s
jrtc27 wrote:
The line above isn't (currently) long enough to warrant wrapping,
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -verify-machineinstrs < %s | \
+; RUN: FileCheck %s
+
+target triple = "riscv64-unknown-linux-gnu"
+
+define dso_local void @foo(i64 %t) local_unnamed
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -verify-machineinstrs < %s | \
+; RUN: FileCheck %s
+
+target triple = "riscv64-unknown-linux-gnu"
jrtc27 wrote:
Convention is to pu
@@ -245,6 +246,7 @@ class DataLayout {
unsigned getDefaultGlobalsAddressSpace() const {
return DefaultGlobalsAddrSpace;
}
+ unsigned getFlatAddressSpace() const { return FlatAddressSpace; }
jrtc27 wrote:
> The absence of this specification indicates t
@@ -0,0 +1,41 @@
+//==- BuiltinsRISCVXCV.td - RISC-V CORE-V Builtin database*- C++
-*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -44,7 +44,7 @@ ArrayRef RISCVTargetInfo::getGCCRegNames()
const {
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
// CSRs
- "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+ "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"
https://github.com/jrtc27 closed
https://github.com/llvm/llvm-project/pull/105726
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jrtc27 wrote:
NB: I would appreciate a review from someone outside the CHERI project
https://github.com/llvm/llvm-project/pull/105726
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https://github.com/jrtc27 updated
https://github.com/llvm/llvm-project/pull/105726
>From cfce8b0d99a088a6a2fb12661a7158786f630802 Mon Sep 17 00:00:00 2001
From: Jessica Clarke
Date: Thu, 22 Aug 2024 21:20:23 +0100
Subject: [PATCH] [CodeGen] Create IFUNCs in the program address space, not
hard-
https://github.com/jrtc27 created
https://github.com/llvm/llvm-project/pull/105726
Commit 0d527e56a5ee ("GlobalIFunc: Make ifunc respect function address
spaces") added support for this within LLVM, but Clang does not properly
honour the target's address spaces when creating IFUNCs, crashing wit
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -std=c++23 -fsyntax-only -verify %s
+//
+// -expected-no-diagnostics
jrtc27 wrote:
?
https://github.com/llvm/llvm-project/pull/96301
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jrtc27 wrote:
Some relevant context for what CPUs we permit merging into LLVM:
https://github.com/llvm/llvm-project/pull/102452#issuecomment-2275962014
How does this apply to NutShell?
https://github.com/llvm/llvm-project/pull/102899
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https://github.com/jrtc27 closed
https://github.com/llvm/llvm-project/pull/101765
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jrtc27 wrote:
For the avoidance of doubt, I would appreciate a review from a core Clang
developer, given Alex also comes from a CHERI LLVM background.
https://github.com/llvm/llvm-project/pull/101765
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https://github.com/jrtc27 created
https://github.com/llvm/llvm-project/pull/101765
ASTContext::getIntWidth returns 1 if isBooleanType(), and falls back on
getTypeSize in the default case, which itself just returns the Width
from getTypeInfo's returned struct, so can be used in all cases here,
no
https://github.com/jrtc27 edited
https://github.com/llvm/llvm-project/pull/100684
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@@ -59,16 +59,26 @@ let TargetPrefix = "riscv" in {
[IntrNoMem, IntrWillReturn, IntrSpeculatable,
ImmArg>, ImmArg>]>;
+ def int_riscv_cv_alu_slet : ScalarCoreVAluGprGprIntrinsic;
jrtc27 wrote:
*Especia
@@ -59,16 +59,26 @@ let TargetPrefix = "riscv" in {
[IntrNoMem, IntrWillReturn, IntrSpeculatable,
ImmArg>, ImmArg>]>;
+ def int_riscv_cv_alu_slet : ScalarCoreVAluGprGprIntrinsic;
jrtc27 wrote:
Is it to
@@ -1240,11 +1240,22 @@ void IRLinker::linkNamedMDNodes() {
if (IsPerformingImport && NMD.getName() == "llvm.stats")
continue;
+// Default subtarget info is only intended to be used before LTO and
+// shouldn't be present after merging because the default sub
jrtc27 wrote:
AFAIK LLD doesn't support Zicfilp yet, which I feel is a prerequisite to
marking it as non-experimental
https://github.com/llvm/llvm-project/pull/98891
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